ATmega16HVB Atmel Corporation, ATmega16HVB Datasheet
ATmega16HVB
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ATmega16HVB Summary of contents
Page 1
... Fully static operation – eight MIPS throughput at 8MHz • High endurance non-volatile memory segments – 16K/32Kbytes of in-system self-programmable flash (Atmel ATmega16HVB/32HVB) – 512/1Kbytes EEPROM – 1K/2Kbytes internal SRAM – Write/erase cycles 10,000 flash/100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C – ...
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... Pin configurations 1.1 TSSOP Figure 1-1. TSSOP - pinout the Atmel ATmega16HVB/32HVB. NI NNI VREFGND VREF GND VREG PA0(ADC0/SGND/PCINT0) PA1(ADC1/SGND/PCINT1) PA2(PCINT2/T0) PA3(PCINT3/T1) VCLMP10 VFET BATT VCC GND RESET/dw PB0(PCINT4/ICP00) PB1(PCINT5/CKOUT) PB2(PCINT6) ATmega16HVB/32HVB ...
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... As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the Atmel ATmega16HVB/32HVB as listed in 1.2.9 Port B (PB7 ...
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... Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in 227. Shorter pulses are not guaranteed to generate a reset. This pin is also used as debugWIRE communication pin. ATmega16HVB/32HVB 4 ”FET driver” on page ”Voltage ADC – 7-channel gen- 116. ” ...
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... Overview The Atmel ATmega16HVB/32HVB is a monitoring and protection circuit for 3- and 4-cell Li-ion applications with focus on highest safety including safe authentication, low cost and high utiliza- tion of the cell energy. The device contains secure authentication features as well as autonomous battery protection during charging and discharging. The External Protection Input ...
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... It is part of the AVR Battery Management family that provides secure authentication, highly accurate monitoring and autonomous protection for Lithium-ion battery cells. The ATmega16HVB/32HVB AVR is supported with a full suite of program and system develop- ment tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and On- chip Debugger. ...
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... Comparison between the Atmel ATmega16HVB and the Atmel ATmega32HVB The ATmega16HVB and the ATmega32HVB differ only in memory size for flash, EEPROM and internal SRAM. Table 2-1. 8042D–AVR–10/11 Table 2-1 summarizes the different configuration for the two devices. Configuration summary. Device Flash ...
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... Data retention Reliability Qualification results show that the projected data retention failure rate is much less than one PPM over 20 years at 85°C or 100 years at 25°C. ATmega16HVB/32HVB 8 1. 8042D–AVR–10/11 ...
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... This allows single-cycle Arithmetic Logic Unit (ALU) operation typ- 8042D–AVR–10/11 Block diagram of the AVR architecture. Program Flash Counter Program Memory Instruction Register Instruction Decoder Control Lines ATmega16HVB/32HVB Data Bus 8-bit Status and Control General Purpose Interrupt Registrers Unit Watchdog Timer ALU ...
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... SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the Atmel ATmega16HVB/32HVB has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...
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... R/W R/W R/W R “Instruction Set Description” for detailed information. ⊕ V “Instruction Set Description” for detailed information. Description” for detailed information. Description” for detailed information. ATmega16HVB/32HVB R/W R/W R/W R Instruction Set Reference. “Instruction “Instruction Set ...
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... The registers R26..R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in ATmega16HVB/32HVB 12 shows the structure of the 32 general purpose working registers in the CPU. ...
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... R/W R/W R/W R/W R/W R/W R/W R/W RAM- RAM- RAM- RAM- END END END END RAM- RAM- RAM- RAM- END END END END ATmega16HVB/32HVB R26 (0x1A R28 (0x1C R30 (0x1E) Instruction Set Reference for details SP11 SP10 SP9 SP8 SP3 SP2 SP1 ...
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... Interrupt Vectors. The complete list of vectors is shown in determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority. ATmega16HVB/32HVB 14 CPU shows the parallel instruction fetches and instruction executions enabled by the Har- The parallel instruction fetches and instruction executions ...
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... SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<<EEMPE); /* start EEPROM write */ EECR |= (1<<EEPE); SREG = cSREG; /* restore SREG value (I-bit) */ 8042D–AVR–10/11 ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ; restore SREG value (I-bit) ATmega16HVB/32HVB 15 ...
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... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. ATmega16HVB/32HVB 16 ; set Global Interrupt Enable 8042D–AVR–10/11 ...
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... This section describes the different memories in the Atmel ATmega16HVB/32HVB. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega16HVB/32HVB features an EEPROM Memory for data storage. All three memory spaces are linear and regular. ...
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... When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the 1K/2Kbytes of internal data SRAM in the ATmega16HVB/32HVB are all accessible through all these addressing modes. The Register File is described in page 12 ...
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... I/O memory The I/O space definition of the ATmega16HVB/32HVB is shown in 255. All ATmega16HVB/32HVB I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these regis- ters, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to ” ...
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... Read/Write Initial Value • Bits 15:10 – Reserved These bits are reserved bits in the ATmega16HVB/32HVB and will always read as zero. • Bits 9:0 – EEAR9:0: EEPROM address The EEPROM Address Registers – EEAR specify the EEPROM address in the 512/1Kbytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 511/1023. ...
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... Initial Value • Bits 7:6 – Reserved These bits are reserved in the Atmel ATmega16HVB/32HVB and will always read as zero. • Bits 5, 4 – EEPM1 and EEPM0: EEPROM programming mode bits The EEPROM Programming mode bit setting defines which programming action that will be trig- gered when writing EEPE ...
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... The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish. ATmega16HVB/32HVB 22 EEPROM programming time. ...
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... EECR,EEMPE ; Start eeprom write by setting EEPE sbi EECR,EEPE ret /* Wait for completion of previous write */ while(EECR & (1<<EEPE Set up address and data registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMPE */ EECR |= (1<<EEMPE); /* Start eeprom write by setting EEPE */ EECR |= (1<<EEPE); ATmega16HVB/32HVB 23 ...
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... GPIOR2 – General purpose I/O Register 2 Bit 0x2B (0x4B) Read/Write Initial Value 8.6.5 GPIOR1 – General purpose I/O Register 1 Bit 0x2A (0x4A) Read/Write Initial Value 8.6.6 GPIOR0 – General purpose I/O Register 0 Bit 0x1E (0x3E) Read/Write Initial Value ATmega16HVB/32HVB 24 r16,EEDR ; MSB R/W R/W R/W R MSB ...
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... The clock systems are detailed below. Clock distribution. Coulomb Counter CPU ADC CORE clk CCADC TWI Disconnect 1/4 Watchdog Timer Battery Protection delay Ultra Low Power VADC ATmega16HVB/32HVB FLASH and Voltage RAM EEPROM ADC clk clk FLASH VADC VADC clk CPU Prescaler AVR ...
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... Clock sources The following section describes the clock sources available in the device. The clocks are input to the AVR clock generator, and routed to the appropriate modules. The Atmel ATmega16HVB/32HVB has three on-board oscillators used to clock the internal logic. Table 9-1 Table 9-1. Calibrated fast RC oscillator ...
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... The actual clock period of the ULP RC Oscillator ULP RC word - ULP RC temp prediction word ULP RC period = --------------------------------------------------------------------------------------------------------------------------------------------------------- ATmega16HVB/32HVB Additional delay from reset, typical values 128ms 256ms 512ms . See Table 9-3 on page 28 and ”Electrical characteris- ” ...
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... System clock prescaler The Atmel ATmega16HVB/32HVB has a System Clock Prescaler, used to prescale the Cali- brated Fast RC Oscillator. The system clock can be divided by setting the Prescale Register” on page clock frequency as the requirement for power consumption and processing power changes. This system clock will affect the clock frequency of the CPU and all synchronous peripherals ...
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... Overview The Oscillator Sampling Interface (OSI) enables sampling of the Slow RC and Ultra Low Power RC (ULP) oscillators in Atmel ATmega16HVB/32HVB. OSI can be used to calibrate the Fast RC Oscillator runtime with high accuracy. OSI can also provide an accurate reference for compen- sating the ULP Oscillator frequency drift. ...
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... CPU, but can be used to trigger the input capture function of Timer/Counter0. Using OSI in combination with the input capture function of Timer/Counter0 facilitates accurate measurement of the oscillator frequencies with a minimum of CPU calcula- tion. Refer to Capture function. ATmega16HVB/32HVB 30 Oscillator sampling interface block diagram. Databus OSICSR ...
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... CPU cycles in n prescaled Slow RC periods number of CPU cycles in n prescaled ULP RC periods ⋅ ------------------------------------------------------------------------------------------------------------------------------------------------ - = ULPRC SlowRC number of CPU cycles in n prescaled Slow RC periods ”Voltage ADC – 7-channel general purpose 12-bit Sigma-Delta ADC” for details. ATmega16HVB/32HVB ”Slow RC oscillator” on page 27 for details. 128 n ⋅ 31 ...
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... Read/Write Initial Value • Bit 5 – CKOE: Clock output When this bit is written to one, the CPU clock divided output on the PB1 pin. 9.8.3 CLKPR – Clock Prescale Register Bit (0x61) Read/Write Initial Value ATmega16HVB/32HVB FCAL7 FCAL6 FCAL5 FCAL4 R/W ...
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... When changing Prescaler value, the VADC Prescaler will automatically change frequency of the VADC clock and abort any ongoing conversion – – – OSISEL0 ATmega16HVB/32HVB 205) determines the initial value of the CLKPS bits. CLKPS0 Clock division factor CLKPS0 VADC division factor ...
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... Bits 7:5, 3:2 – Reserved These bits are reserved in the Atmel ATmega16HVB/32HVB and will always read as zero. • Bit 4 – OSISEL0: Oscillator sampling interface select 0 Table 9-6. • Bit 1 – OSIST: Oscillator sampling interface status This bit continuously displays the phase of the prescaled clock. This bit can be polled by the CPU to determine the rising and falling edges of the prescaled clock. • ...
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... SRAM are unaltered when the device wakes up from any sleep mode except Power-off reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. 8042D–AVR–10/11 presents the different clock systems in the Atmel ATmega16HVB/32HVB, Wake-up sources X ...
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... Active modules in different sleep modes. Module RCOSC_FAST RCOSC_ULP RCOSC_SLOW OSI CPU Flash 8-bit Timer/16-bit Timer TWI/SMBus SPI V-ADC CC-ADC ATmega16HVB/32HVB 36 Reset From all States Except Power-on Reset Reset Time-out Sleep Interrupt Idle Black-out Detection Charger Connected ADC noise Active Idle ...
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... and clk , while allowing the other clocks to run. Idle mode enables the CPU FLASH , and clk , while allowing the other clocks to run. CPU FLASH ATmega16HVB/32HVB Mode ADC noise reduction Power-save ( ...
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... In sleep modes where both the I/O clock (clk be disabled. This ensures that no power is consumed by the input logic when not needed. In ATmega16HVB/32HVB 38 1. Before entering Power-off sleep mode, interrupts should be disabled by software. Otherwise interrupts may prevent the SLEEP instruction from being executed within the time limit. ...
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... Battery Protection Control Register” on page for details – – – – ATmega16HVB/32HVB for details on 138. The current consump- for details on for details on CC- ”Voltage reference and temperature sen SM2 SM1 SM0 SE R/W R/W R/W R/W ...
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... Bits 7:4 – Reserved These bits are reserved in the Atmel ATmega16HVB/32HVB, and will always read as zero. • Bits 3:1 – SM2:0: Sleep Mode Select Bits 2, 1 and 0 These bits select between the four available sleep modes as shown in Table 10-3. SM2 • Bit 0 – SE: Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’ ...
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... Bit 0 – PRVADC: Power Reduction V-ADC Writing a logic one to this bit shuts down the V-ADC. Before writing the PRVADC bit, make sure that the VADEN bit is cleared to minimize the power consumption. Note: 8042D–AVR–10/11 V-ADC control registers can be updated even if the PRVADC bit is set. ATmega16HVB/32HVB 41 ...
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... Reset sources The Atmel ATmega16HVB/32HVB has five sources of reset: • The Power-on Reset module generates a Power-on Reset when the Voltage Regulator starts up • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length • ...
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... Timer Ultra Low Power RC Oscillator Clock Generator SUT[1:0] , the Voltage Regulator starts up and the chip enters RESET mode. When the POT ”Charger detect” on page ATmega16HVB/32HVB DATA BUS MCU Status Register (MCUSR) POR COUNTER RESET Delay Counters TIMEOUT CK . When the voltage at the BATT pin ...
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... Figure 11-2. Powering up Atmel ATmega16HVB/32HVB. 11.2.2 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – V MCU after the Time-out period – ...
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... Figure 11-4. Watchdog reset during operation. 11.2.4 Brown-out detection Atmel ATmega16HVB/32HVB has an On-chip Brown-out Detection (BOD) circuit for monitoring the hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V The BOD is automatically enabled in all modes of operation, except in Power-off mode. ...
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... Possible hardware fuse watchdog always on (WDTON) for fail-safe mode 11.4.2 Overview Atmel ATmega16HVB/32HVB has an Enhanced Watchdog Timer (WDT). The WDT counts cycles of the Ultra Low Power RC Oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode required that the sys- tem uses the WDR - Watchdog Timer Reset - instruction to restart the counter before the time- out value is reached ...
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... Turn on global interrupt sei ret (1) __disable_interrupt(); __watchdog_reset(); /* Clear WDRF in MCUSR */ MCUSR &= ~(1<<WDRF); /* Write logical one to WDCE and WDE */ /* Keep old prescaler setting to prevent unintentional time-out */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCSR = 0x00; __enable_interrupt(); 1. See ”About code examples” on page ATmega16HVB/32HVB 8. 47 ...
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... Note: Note: The Watchdog Timer should be reset before any change of the WDP bits, since a change in the WDP bits can result in a time-out when switching to a shorter time-out period. ATmega16HVB/32HVB 48 If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay enabled ...
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... Read/Write Initial Value • Bits 7:5 – Reserved These bits are reserved in the Atmel ATmega16HVB/32HVB, and will always read as zero. • Bit 4 – OCDRF: OCD Reset Flag This bit is set if a debugWIRE Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • ...
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... Bits 5, 2:0 – WDP3:0: Watchdog Timer Prescaler three, two, one, and null The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in Table 11-2 on page ATmega16HVB/32HVB 50 Watchdog timer configuration. (1) ...
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... The actual timeout value depends on the actual clock period of the Ultra Low Power RC Oscil- lator, refer to ”Ultra Low Power RC oscillator” on page 2. Due to synchronization logic in the Watchdog timer, the time between two consecutive WDT time-outs will be three cycles longer than the numbers listed. ATmega16HVB/32HVB Number of WDT Typical oscillator cycles timeout ...
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... Interrupts 12.1 Overview This section describes the specifics of the interrupt handling as performed in Atmel ATmega16HVB/32HVB. For a general explanation of the AVR interrupt handling, refer to and interrupt handling” on page 12.2 Interrupt vectors in Atmel ATmega16HVB/32HVB Table 12-1. Vector No ...
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... Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 12-2. BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in Atmel ATmega16HVB/32HVB is: Address Labels Code 0x0000 jmp ...
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... Reset and Interrupt Vector Addresses is: Address Labels Code .org 0x0002 0x0002 jmp 0x0004 jmp ATmega16HVB/32HVB 54 ; Timer1 Compare B Handler ; Timer1 Overflow Handler ; Timer0 Input Capture Handler ; Timer0 CompareA Handler ; Timer0 CompareB Handler ; Timer0 Overflow Handler ; Two-wire Bus Connect/Disconnect Handler ...
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... SPL,r16 ; Enable interrupts xxx Comments RESET ; Reset handler BPINT ; Battery Protection Interrupt Handler EXT_INT0 ; External Interrupt Request 0 Handler ... ; SPM_RDY ; Store Program Memory Ready Handler r16,high(RAMEND); Main program start SPH,r16 ; Set Stack Pointer to top of RAM r16,low(RAMEND) SPL,r16 ; Enable interrupts xxx ATmega16HVB/32HVB 55 ...
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... Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling. Note: ATmega16HVB/32HVB JTD – ...
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... IVSEL description above. See Code Example in rupts between application and boot space” on page 8042D–AVR–10/11 executing from the Boot Loader section. Refer to the section write self-programming” on page 188 ATmega16HVB/32HVB ”Boot loader support – Read-while- for details on Boot Lock bits. 56. ”Moving inter- ...
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... Enable bit in the EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Regis- ter before the interrupt is re-enabled. ATmega16HVB/32HVB 58 “EICRA – External Interrupt Control Register A” ...
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... Initial Value • Bits 7:4 – Reserved These bits are reserved ins the Atmel ATmega16HVB/32HVB, and will always read as zero. • Bits 3:0 – INT3 – INT0: External Interrupt Request 3:0 enable When an INT3 – INT0 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt Control Register – ...
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... Initial Value • Bits 7:2 – Reserved These bits are reserved in the Atmel ATmega16HVB/32HVB, and will always read as zero. • Bit 1 – PCIE1: Pin Change Interrupt Enable 1 When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is enabled ...
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... Read/Write Initial Value • Bits 7:4 – Reserved These bits are reserved in the Atmel ATmega16HVB/32HVB, and will always read as zero. • Bit 3:0 – PCINT[3:0]: Pin Change Enable Mask 3:0 Each PCINT[3:0] bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT[3:0] is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin ...
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... I/O Registers and bit locations are listed in One I/O Memory address location is allocated for each high voltage port, the Data Register – PORTx. The Data Register is read/write. Using the I/O port as General Digital Output is described in I/O” on page ATmega16HVB/32HVB 62 for a complete list of parameters. Pxn C pin ” ...
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... WRx, RRx and RPx are common to all pins within the same port. clk mon to all ports. 2. The High Voltage Digital Input is not present on PC5. 66, the PORTxn bits are accesed at the PORTx I/O address, and the PINxn bits at the ATmega16HVB/32HVB shows a functional description of one output port (1) . ...
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... The High Voltage I/O has alternate port functions in addition to being general digital I/O. 14-3 shows how the port pin control signals from the simplified overridden by alternate functions. Figure 14-3. High voltage digital I/O Notes: Table 14-1 on page 65 indexes from generated internally in the modules having the alternate function. ATmega16HVB/32HVB 64 (1)(2) . Pxn DIEOExn DIEOVxn 1 0 ...
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... Port C pins alternate functions. Alternate function PC0 INT0/ EXTPROT(External Interrupt 0 or External Battery Protection Input) PC1 INT1 (External Interrupt 1) PC2 INT1 (External Interrupt 2) PC3 INT3/ SDA (External Interrupt bus data line) PC4 SCL (SM Bus Clock line) ATmega16HVB/32HVB Table 14-2. 65 ...
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... Bit 0x08 (0x28) Read/Write Initial Value 14.5.2 PINC – Port C Input Pins Address Bit 0x06 (0x26) Read/Write Initial Value ATmega16HVB/32HVB 66 relates the alternate functions of Port C to the overriding signals shown in 64. PC3/INT3/SDA PC2/INT2 SM BUS ENABLED SM BUS DATA INT3 ENABLE INT2 ENABLE SM BUS ENABLED ...
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... Pxn C pin ”Register description” on page 68. Many low voltage port pins are multiplexed with alternate functions for the periph- 72. Refer to the individual module sections for a full descrip- ATmega16HVB/32HVB and Ground REG for a complete list Logic See Figure " ...
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... If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). ATmega16HVB/32HVB 68 Pxn PUD: ...
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... Input 1 1 Input 0 X Output 1 X Output Figure 15-2 on page shows a timing diagram of the synchronization when reading an externally applied pin ATmega16HVB/32HVB Pull-up Comment No Tri-state (Hi-Z) Yes Pxn will source current if ext. pulled low No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) 68, the PINxn Register bit and the preced- ...
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... The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. ATmega16HVB/32HVB 70 SYSTEM CLK ...
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... Figure 15-2 on page 68, the digital input signal can be clamped to ground at the ”Alternate port functions” on page ATmega16HVB/32HVB /2. REG 72. 71 ...
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... AVR microcon- troller family. Figure 15-5. Alternate port functions Note: ATmega16HVB/32HVB 72 or GND is not recommended, since this may cause excessive currents if the pin is CC shows how the port pin control signals from the simplified (1) ...
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... Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer This is the Analog Input/output to/from alternate functions. The Analog signal is connected directly to the pad, and can be used bi- input/output directionally ATmega16HVB/32HVB Fig- 73 ...
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... T1/PCINT3 – Port A, Bit3 T1: Timer/Counter1. This pin can serve as Timer/Counter1 clock source. PCINT3: Pin Change Interrupt 3. These pins can serve as external interrupt source. functions of Port A to the overriding signals shown in ATmega16HVB/32HVB 74 Port A pins alternate functions. Port pin Alternate function PA3 ...
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... SCK/PCINT9 (SPI Bus Serial Clock or Pin Change Interrupt 9) SS/PCINT8 (SPI Bus Slave Select input or Pin Change Interrupt 8) PCINT7 (Pin Change Interrupt 7) PCINT6 (Pin Change Interrupt 6) CKOUT/PCINT5 (Clock output or Pin Change Interrupt 5) PCINT4/ICP00 (Pin Change Interrupt 4 or Timer/Counter0 Input Capture Trigger) ATmega16HVB/32HVB PA0/ADC0/SGND/PCINT0 VADSC • ...
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... PCINT5: Pin Change Interrupt 5. This pin can serve as external interrupt source. • ICP00/PCINT4 – Port B, Bit0 ICP00: Input Capture Timer/Counter0. This pin can serve as Input Capture Trigger for Timer/Counter0. PCINT4: Pin Change Interrupt 4. This pin can serve as external interrupt source. ATmega16HVB/32HVB 76 28. 8042D–AVR–10/11 ...
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... PCINT7 • PCIE1 PCINT6 • PCIE1 1 1 PCINT7 INPUT PCINT6 INPUT – – ATmega16HVB/32HVB PB5/SCK/PCINT9 PB4/SS/PCINT8 SPE • MSTR SPE • MSTR PORTB5 • PUD PORTB0 • PUD SPE • MSTR SPE • MSTR 0 SPE • MSTR SCK OUTPUT – ...
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... PORTB – Port B Data Register Bit 0x05 (0x25) Read/Write Initial Value 15.4.6 DDRB – Port B Data Direction Register Bit 0x04 (0x24) Read/Write Initial Value 15.4.7 PINB – Port B Input Pins Address Bit 0x03 (0x23) Read/Write Initial Value ATmega16HVB/32HVB – – CKOE PUD R R R/W R for more details about this feature ...
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... A prescaler reset will affect the prescaler period for all Timer/Counters it is connected to. Figure 16-1. Prescaler for timer/counter. 8042D–AVR–10/11 ). Alternatively, one of four taps from the prescaler can be used as a CLK_I/O clk I/O Clear PSRSYNC Tn Synchronization ATmega16HVB/32HVB /8, f /64, f CLK_I/O CLK_I/O CSn0 CSn1 CSn2 n clk Tn /256, or ...
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... However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances recommended that maximum frequency of an external clock source is less than f An external clock source can not be prescaled. Note: ATmega16HVB/32HVB 80 pulse for each positive (CSn2 negative (CSn2 ...
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... I External clock source on Tn pin. Clock on falling edge 1 1 External clock source on Tn pin. Clock on rising edge TSM – – – R ATmega16HVB/32HVB – CSn2 CSn1 CSn0 R R/W R/W R – – – ...
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... Timer/Counter general purpose 8-bit/16-bit Timer/Counter module, with two/one Output Compare units and Input Capture feature. The Atmel ATmega16HVB/32HVB has two Timer/Counters, Tim er/Counter0 and Timer/Counter1. The functionality for both Timer/Counters is described below. Timer/Counter0 and Timer/Counter1 have different Timer/Counter registers, as shown in page 255 ...
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... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF/0xFFFF (MAX) or the value stored in the OCRnA Register ”Timer/Counter0 and Timer/Counter1 prescalers” on DATA BUS count TCNTn Control Logic ATmega16HVB/32HVB ). Tn Figure 17-2 shows a block diagram TOVn (Int.Req.) Clock Select ...
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... Clear timer on Compare Match (CTC) 8-bit mode In Clear Timer on Compare or CTC mode, the OCRnA Register is used to manipulate the coun- ter resolution, see ATmega16HVB/32HVB 84 Increment or decrement TCNTn by one Timer/Counter clock, referred to as clk Tn Signalize that TCNTn has reached maximum value ” ...
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... TCNTn Period 1 2 for bit settings. The Overflow Flag (TOVn) will be set in the same timer clock Table 17-2 on page 84 for bit settings. In CTC mode the counter is cleared to ATmega16HVB/32HVB Figure 17-3. The counter value (TCNTn) OCnx Interrupt Flag Set 3 4 Table 85 ...
Page 86
... Output Compare Register OCRnB is free to be used as a normal Output Compare Register, but in 16-bit Input Capture mode the Output Compare Unit cannot be used as there are no free Output Compare Register(s). Even though the Input Capture register is called ICRn in this sec- ATmega16HVB/32HVB 86 “Input capture unit” ...
Page 87
... Register has been read. After a change of the edge, the Input Capture Flag (ICFn) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the trigger edge change is not required. 8042D–AVR–10/11 ATmega16HVB/32HVB ”Accessing registers in 16-bit mode” on page 90. 87 ...
Page 88
... All CPU write operations to the TCNTnH/L Register will block any Compare Match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCRnA initialized to the same value as TCNTn without triggering an interrupt when the Timer/Counter clock is enabled. ATmega16HVB/32HVB 88 Timer/Counter0 Input Capture Source (ICS). Source ...
Page 89
... I/O clk Tn (clk /8) I/O TCNTn MAX - 1 TOVn shows the setting of OCFnA and OCFnB in Normal mode. clk I/O clk Tn (clk /8) I/O TCNTn OCRnx - 1 OCRnx OCFnx ATmega16HVB/32HVB ) is therefore shown MAX BOTTOM BOTTOM + 1 /8). clk_I/O MAX BOTTOM BOTTOM + 1 OCRnx OCRnx + 1 OCRnx Value /8). clk_I/O OCRnx + 2 89 ...
Page 90
... 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the high byte. ATmega16HVB/32HVB 90 shows the setting of OCFnA and the clearing of TCNTn in CTC mode. clk ...
Page 91
... Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNTnH,r17 out TCNTnL,r16 ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ... unsigned int i; ... /* Set TCNTn to 0x01FF */ TCNTn = 0x1FF; /* Read TCNTn into TCNTn; ... 1. See ”About code examples” on page ATmega16HVB/32HVB 8. 91 ...
Page 92
... SREG; /* Disable interrupts */ _CLI(); /* Read TCNTn into TCNTn; /* Restore global interrupt flag */ SREG = sreg; return i; } Note: The assembly code example returns the TCNTnH/L value in the r17:r16 register pair. ATmega16HVB/32HVB 92 1. See ”About code examples” on page 8. 8042D–AVR–10/11 ...
Page 93
... TCNTnL,r16 ; Restore global interrupt flag out SREG,r18 ret unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNTn TCNTn = i; /* Restore global interrupt flag */ SREG = sreg; 1. See ”About code examples” on page ATmega16HVB/32HVB 8. 93 ...
Page 94
... See • Bits 2:1 – Reserved These bits are reserved in the Atmel ATmega16HVB/32HVB and will always read as zero. • Bit 0 – WGMn0: Waveform Generation Mode This bit controls the counting sequence of the counter, the source for maximum (TOP) counter ...
Page 95
... R/W R TCNTnH[7:0] R/W R/W R/W R ”Accessing registers in 16-bit mode” on page OCRnA[7:0] R/W R/W R OCRnB[7:0] R/W R/W R/W R ATmega16HVB/32HVB R/W R/W R/W R R/W R/W R R/W R/W R/W R ”Accessing registers in 16 R/W R/W R/W R/W 0 ...
Page 96
... Bits 3 – ICFn: Timer/Counter n Input Capture Flag This flag is set when a capture event occurs, according to the setting of ICENn, ICESn and ICSn bits in the TCCRnA Register. ICFn is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICFn can be cleared by writing a logic one to its bit location. ATmega16HVB/32HVB 96 90 ...
Page 97
... The bit TOVn is set when an overflow occurs in Timer/Counter n. TOVn is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOVn is cleared by writing a logic one to the flag. When the SREG I-bit, TOIEn (Timer/Counter n Overflow Interrupt Enable), and TOVn are set, the Timer/Counter n Overflow interrupt is executed. 8042D–AVR–10/11 ATmega16HVB/32HVB 97 ...
Page 98
... Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the Atmel ATmega16HVB/32HVB and peripheral devices or between several AVR devices. When the SPI is not used, power consumption can be minimized by writing the PRSPI bit in PRR0 to one. See the PRSPI bit. ...
Page 99
... When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to ”Alternate port functions” on page 8042D–AVR–10/11 Table 18-1 on page 100. For more details on automatic port overrides, refer to 72. ATmega16HVB/32HVB Figure 18-2. The sys- SHIFT ENABLE /4. osc ...
Page 100
... DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins, for example, if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB. ATmega16HVB/32HVB 100 (1) SPI pin overrides ...
Page 101
... Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; 1. See ”About code examples” on page ATmega16HVB/32HVB 8. 101 ...
Page 102
... Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); } char SPI_SlaveReceive(void Wait for reception complete */ while(!(SPSR & (1<<SPIF))) /* Return Data Register */ return SPDR; } Note: ATmega16HVB/32HVB 102 (1) r17,(1<<DD_MISO) DDR_SPI,r17 r17,(1<<SPE) SPCR,r17 r16,SPDR ( See ”About code examples” on page 8. ...
Page 103
... Table 18-3 on page 105 SPI modes. Conditions 0 CPOL=0, CPHA=0 1 CPOL=0, CPHA=1 2 CPOL=1, CPHA=0 3 CPOL=1, CPHA=1 ATmega16HVB/32HVB 104. Data bits are shifted out and latched in on and Table 18-4 on page Leading edge Trailing edge Sample (Rising) Setup (Falling) Setup (Rising) Sample (Falling) Sample (Falling) ...
Page 104
... Figure 18-3. SPI transfer format with CPHA = 0. Figure 18-4. SPI transfer format with CPHA = 1. ATmega16HVB/32HVB 104 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 Bit 5 LSB first (DORD = 1) LSB Bit 1 Bit 2 SCK (CPOL = 0) ...
Page 105
... Figure 18-3 on page 104 and CPOL functionality. CPOL Leading edge 0 Rising 1 Falling Figure 18-3 on page 104 CPHA functionality. CPHA Leading edge 0 Sample 1 Setup ATmega16HVB/32HVB CPOL CPHA SPR1 SPR0 R/W R/W R/W R Figure 18-4 on page 104 for an example. The Trailing edge Falling ...
Page 106
... SPI Data Register. • Bit 5:1 – Reserved These bits are reserved in the Atmel ATmega16HVB/32HVB and will always read as zero. • Bit 0 – SPI2X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see clock periods ...
Page 107
... The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis- ter causes the Shift Register Receive buffer to be read. 8042D–AVR–10/ MSB R/W R/W R/W R ATmega16HVB/32HVB LSB R/W R/W R/W R SPDR Undefined 107 ...
Page 108
... The CC-ADC has a programmable voltage range allowing trade-off to be made between resolu- tion, dynamic range and external sense resistor RSENSE. In normal conversion mode two different output values are provided, Instantaneous Current and Accumulate Current. The Instantaneous Current Output has a short conversion time at the cost ATmega16HVB/32HVB 108 8-BIT DATABUS Instantaneous ...
Page 109
... DATA4 will be lost because DATA3 reading is not completed within the limited period. 8042D–AVR–10/11 . Running in normal conversion mode, two data conversion outputs are provided. ~12 ms settling INVALID DATA Figure 19-3 on page 110 ATmega16HVB/32HVB Figure 19-2 3.9 ms 3.9 ms 7.8 ms DATA 1 DATA 2 DATA 3 ...
Page 110
... The CC-ADC offers Polarity Switching for internal offset canceling. By switching the polarity of the sampled input signal at selected time intervals, the internal voltage offset of the CC-ADC will cancel at the output. This feature prevents the CC-ADC from accumulating an offset error over time. ATmega16HVB/32HVB 110 settling INVALID DATA illustrates the Regular Current Detection Mode ...
Page 111
... Low Power RC oscillator” on page ”System clock and clock options” on page CADEN CADPOL CADUB CADAS1 R/W R 122. ATmega16HVB/32HVB 122. 27), and will depend on its actual frequency. To for details CADAS0 CADSI1 CADSI0 R/W R/W R ...
Page 112
... Initial Value • Bits 7, 3 – Reserved These bits are reserved in the Atmel ATmega16HVB/32HVB and will always read as zero. • Bit 6 – CADACIE: CC-ADC Accumulate Current Interrupt Enable When the CADACIE bit is set (one), and the I-bit in the Status Register is set (one), the CC-ADC Accumulate Current Interrupt is enabled ...
Page 113
... Table 19-3 on page 113 Input voltage range and the conversion value step-size for the CADVSE settings. Voltage range 0 ±200mV 1 ±100mV ATmega16HVB/32HVB – – – – shows the Input Voltage Range and the conversion ...
Page 114
... Reading the registers in the sequence CADAC0, CADAC1, CADAC2, CADAC3 will ensure that consistent values are read. When a conversion is completed, all four registers must be read before the next conversion is completed, otherwise data will be lost. 19.7.6 CADRCC – CC-ADC regular charge current Bit (0xE9) Read/Write Initial Value ATmega16HVB/32HVB 114 CADIC[15:8] CADIC[7:0] 7 ...
Page 115
... R/W R/W R 115. Programmable range for the regular discharge current level 1mΩ SENSE R = 5mΩ SENSE R = 10mΩ SENSE Values in the table are shown with the CADVSE set to both 0 and 1. ATmega16HVB/32HVB (1) . Minimum Maximum 0 13696/6848 0 13696/6848 0 2740/1370 0 1370/685 CADRDC[7:0] R/W ...
Page 116
... Interrupt on V-ADC conversion complete 20.2 Overview The Atmel ATmega16HVB/32HVB features a 12-bit Sigma-Delta ADC. The Voltage ADC (V-ADC) is connected to seven different sources through the Input Multi- plexer. There are four differential channels for Cell Voltage measurements. These channels are scaled 0.2× to comply with the Full Scale range of the V-ADC. In addition there are three single ended channels referenced to SGND ...
Page 117
... SGND 8042D–AVR–10/11 ”Bandgap calibration” on page 519µs Start Conversion Interrupt OLD DATA INVALID DATA 220. Both thermistors, RT32 and RT33 are connected through a common ATmega16HVB/32HVB 123 ATA ”Operating circuit” on page INVALID DATA ”Operat- 117 ...
Page 118
... Figure 20-3. A 3-cell mode connection. ATmega16HVB/32HVB 118 151) for details for balancing the battery cells. When balancing a cell ”Cell balancing” on page 151 Figure R PV4 R PV3 C R PV2 ATmega16HVB/32HVB C R PV1 for details. 20-3. Note that even if the input is 8042D–AVR–10/11 ...
Page 119
... Bit (0x7C) Read/Write Initial Value • Bit 7:4 – Reserved These bits are reserved in the Atmel ATmega16HVB/32HVB and will always read as zero. • Bit 3:0 – VADMUX[3:0]: V-ADC Channel Selection Bits The VADMUX bits determine the V-ADC channel selection. See Table 20-1. 20.4.2 VADCSR – V-ADC Control and Status Register ...
Page 120
... These bits represent the result from the conversion. To obtain the best absolute accuracy for the cell voltage measurements, gain and offset com- pensation is required. Factory calibration values are stored in the device signature row, refer to section mV is given by: The voltage on the ADCn is given by: ADCn[mV] ATmega16HVB/32HVB 120 – – ...
Page 121
... The absolute temperature in Kelvin is given by: VADCH/L VPTAT CAL T(K) = -------------------------------------------------------------- - – – – ATmega16HVB/32HVB ”Reading the signature row from software” on ⋅ 16384 – – – PA1DID R ...
Page 122
... Low power consumption 21.2 Overview The Atmel ATmega16HVB/32HVB features a highly accurate low power On-chip Bandgap Ref- erence Voltage, VREF of 1.100V. This reference voltage is used as reference for the On-chip Voltage Regulator, the Brown-out Detector, the internal Cell Balancing, the Battery Protection, the V-ADC and the CC-ADC. ...
Page 123
... Settling time is needed when the Buffer is enabled by software, or after a reset condition. 8042D–AVR–10/11 . for details. See ”Electrical characteristics” on page 225 ATmega16HVB/32HVB ”Reading the signature ”Electrical characteristics” on page 225 ”Register description” on page 124 for details on hold-off time. for ...
Page 124
... VREF curve to the lowest possible temperature. The application software should read the Atmel factory calibration value and store it to the BGCRR register. See ware” on page 195 ATmega16HVB/32HVB 124 7 6 ...
Page 125
... External Decoupling Pin for the Voltage Reference. 8042D–AVR–10/ – – BGD BGSCDE R R R/W R ”Bandgap buffer settling time” on page ATmega16HVB/32HVB – – BGSCDIF BGSCDIE R R R/W R 123. BGCSR 125 ...
Page 126
... Overview The Charger Detect module has two main functions: • Control the device operating state (power-off or normal operation) • Detect when a charger is connected/disconnected Figure 22-1 Figure 22-1. Charger Detect block diagram. ATmega16HVB/32HVB 126 shows a block diagram of the Charger Detect module. VFET DFET_EN BLOD ...
Page 127
... VPOT, before the chip is able to re-enable the Voltage Regulator and start-up the device. 22.3.2 Interrupt logic When the ATmega16HVB/32HVB is running in normal operation mode, the Charger Detect is capable of giving an interrupt to the CPU if a charger is connected/disconnected or both. Inter- rupt is enabled/disabled by writing to the CHGDIE bit in the Control and Status Register” on page Interrupt is given when a charger is connected, disconnected or both depending on interrupt sense control settings ...
Page 128
... CHGDIF recommended to write this bit to one when setting CHGDIE. • Bit 0 – CHGDIE: Charger Detect Interrupt Enable When the CHGDIE bit is set (one), and the I-bit in the Status Register is set (one), the Charger Detect Interrupt is enabled. ATmega16HVB/32HVB 128 – ...
Page 129
... Overview The Atmel ATmega16HVB/32HVB get its voltage supply through the VFET terminal. Operating range at the VFET terminal 18V. The on-chip LDO regulator regulates the VFET terminal down to 3.3V, which is a suitable supply voltage for the internal logic, I/O lines and analog cir- cuitry ...
Page 130
... To ensure that the internal logic has safe operating condition, the Voltage Regulator has built-in Black-Out Detector (BLOD). If the voltage at the VREG pin drops below the Black-out Detection Level, V ATmega16HVB/32HVB 130 ”Charger detect” on page 225, the Voltage Regulator enters the Battery Pack Short mode. In this application note AVR132 , the chip will automatically enter Power-off mode ...
Page 131
... Bit 0 – ROCWIE: ROC Warning Interrupt Enable The ROCWIE bit enables interrupt caused by the Regulator Operating Condition Warning inter- rupt flag. 8042D–AVR–10/ ROCS – – ROCD R ATmega16HVB/32HVB – – ROCWIF ROCWIE R R R/W R ROCR 131 ...
Page 132
... Effect of battery protection types. Battery protection type Interrupt requests Short-circuit Protection Discharge Over-current Protection Charge Over-current Protection Discharge High-current Protection Charge High-current Protection External Protection Input Entry and/or Exit ATmega16HVB/32HVB 132 PC-FET C-FET Entry Operational Disabled Entry Operational Disabled Entry Operational Disabled Entry ...
Page 133
... Charge Over-current Protection will be acti- vated again. 24.3.4 Discharge high-current protection If the voltage at the PPI/NNI pins is above the Discharge High-current Detection level for a time longer than High-current Protection Reaction Time, the chip activates Discharge High-current Protection. 8042D–AVR–10/11 ATmega16HVB/32HVB 133 ...
Page 134
... Note that the External Protection Input is default enabled. This means that after reset (and dur- ing reset) the port is default overridden to digital input, independent of the port register setting. ATmega16HVB/32HVB 134 ”Register description” on page 137 62 ...
Page 135
... External Protection condition disappears. Figure 24-1. External protection input example [CFE [DFE INT0 8042D–AVR–10/11 220). However if the SW does not take any action, the C-FET and D-FET will be ATmega16HVB/32HVB ”Operating cir- 135 ...
Page 136
... Also note that none of the current protections are deactivated by the External Protection Input. To save power during an External Protection event, DFE and CFE in the FCSR register should be cleared and make sure that the chip is not operating in DUVR mode. ATmega16HVB/32HVB 136 8042D–AVR–10/11 ...
Page 137
... Battery Protection Level Register Timing Register Current PPI Battery NNI Protection EXTPROT – – – ATmega16HVB/32HVB Figure 24-2. 8-BIT DATA BUS 10 Interrupt Request LOCK? Interrupt Acknowledge Battery Protection Control Register Battery Protection Interrupt Register Current Protection Control Power-off 4 ...
Page 138
... High-current Detection will be disabled, and any Discharge High-current condition will be ignored. • Bit 0 – CHCD: Charge High-current Protection Disable When the CHCD bit is set, the Charge High-current Protection is disabled. The Charge High-cur- rent Detection will be disabled, and any Charge High-current condition will be ignored. Note: ATmega16HVB/32HVB 138 – ...
Page 139
... Read/Write Initial Value • Bit 7 – Reserved This bit is reserved in the Atmel ATmega16HVB/32HVB and will always read as zero. • Bit 6:0 – SCPT[6:0]: Short-current Protection Timing These bits control the delay of the Short-circuit Protection. The Short-circuit Timing can be set with a step size of 62.5µs as shown in Table 24-2 ...
Page 140
... Read/Write Initial Value • Bit 7:6 – Reserved These bits are reserved in the Atmel ATmega16HVB/32HVB and will always read as zero. • Bit 5:0 – HCPT[5:0]: High-current protection timing These bits control the delay of the High-circuit Protection. The High-current Timing can be set with a step size shown in Table 24-4 ...
Page 141
... Due to synchronization of parameters between clock domains, a guard time of three ULP oscilla- tor cycles plus three CPU clock cycles is required between each time the BPDOCD register is written. Any writing to the BPDOCD register during this period will be ignored. ATmega16HVB/32HVB (1) ... (122ms - 124ms (124ms - 126ms ” ...
Page 142
... Note: 24.7.10 BPCHCD – Battery Protection Charge-High-current Detection Level Register Bit (0xF9) Read/Write Initial Value • Bits 7:0 –CHCDL[7:0]: Charge High-current Detection Level These bits sets the R Table 24-5. Note: Table 24-5. ATmega16HVB/32HVB 142 R/W R/W R voltage level for detection of Charge Over-current, as defined in SENSE ...
Page 143
... All other values – – – SCIE R ATmega16HVB/32HVB voltage levels for all current detection level 100 110 120 130 140 150 170 190 210 230 250 ...
Page 144
... Once Discharge High-current violation is detected, DHCIF becomes set. The flag is cleared by writing a logic one to it. • Bit 0 – CHCIF: Charge High-current Protection Activated Interrupt Once Charge High-current violation is detected, CHCIF becomes set. The flag is cleared by writ- ing a logic one to it. ATmega16HVB/32HVB 144 – ...
Page 145
... Overview The Atmel ATmega16HVB/32HVB integrates an N-channel FET driver for turning on and off external high-side Charge and Discharge FETs in Li-ion battery packs. The FET driver is designed for outputting a high voltage gate overdrive of typically 13V during normal operation. ...
Page 146
... If such conditions occur, software is not allowed to turn on the FETs until the current condition has normalized. To charge deeply discharged cells the ATmega16HVB/32HVB can be configured to run in Deep Under Voltage Recovery (DUVR) mode. Using chargers with pre-charge current functionality, this allows charging of deeply discharge cells without an additional pre-charge FET. For char- gers without a pre-charge limitation current, an optional pre-charge FET in parallel with a charge FET is supported to be able to charge deeply discharge cells ...
Page 147
... DUVR mode and enable the C-FET before the charger sees this limit. 8042D–AVR–10/11 ATmega16HVB/32HVB ”Deep under voltage operation with pre-charge FET” on page 149), and enable the C-FET by setting the CFE bit. ”Coulomb counter – Dedicated fuel gauging 108 ...
Page 148
... A charger with 12.6V charge voltage is plugged to the Pack+ pin and the Atmel ATmega16HVB/32HVB enters reset mode. Charger should be configured with a charge current limit (pre-charge current). 2. The ATmega16HVB/32HVB exit reset and initializes modules. To determine if charging should be allowed and if DUVR mode should be entered, cell temperature and cell volt- ages are measured by the V-ADC. ...
Page 149
... Read/Write Initial Value • Bits 7:4 – Reserved These bits are reserved in the Atmel ATmega16HVB/32HVB, and will always read as zero. • Bit 3 – DUVRD: Deep Under-voltage Recovery Disabled When the DUVRD is cleared (zero), the FET Driver will be forced to operate in Deep Under-volt- age Recovery DUVR mode. See charge FET” ...
Page 150
... DUVRD bit is cleared, the charge FET will be enabled by DUVR mode regardless of the CFE status. Notes: ATmega16HVB/32HVB 150 1. Due to synchronization of parameters between clock domains, a guard time of three ULP oscil- lator cycles plus three CPU clock cycles is required between each time the FCSR register is written ...
Page 151
... Cell balancing 26.1 Overview The Atmel ATmega16HVB/32HVB incorporates cell balancing FETs. The chip provides one cell balancing FET for each battery cell in series. The FETs are directly controlled by the application software, allowing the cell balancing algorithms to be implemented in software. The FETs are connected in parallel with the individual battery cells ...
Page 152
... Read/Write Initial Value • Bit 7:4 – Reserved These bits are reserved in the Atmel ATmega16HVB/32HVB and will always read as zero. • Bit 3 – CBE4: Cell Balancing Enable 4 When this bit is set, the integrated Cell Balancing FET between terminals PV4 and PV3 will be enabled ...
Page 153
... When the TWI is not used, power consumption can be minimized by writing the PRTWI bit in PRR0 to one. See the PRTWI bit. Figure 27-1. TWI bus interconnection. 8042D–AVR–10/11 ”PRR0 – Power Reduction Register 0” on page 40 Device 1 Device 2 Device 3 SDA SCL ATmega16HVB/32HVB for details on how to use V BUS ........ Device 153 ...
Page 154
... Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level of the data line must be stable when the clock line is high. The only exception to this rule is for generating start and stop conditions. Figure 27-2. Data validity. ATmega16HVB/32HVB 154 TWI terminology. Description The device that initiates and terminates a transmission ...
Page 155
... Note that transmitting the general call address followed by a Read bit is meaningless, as this would cause contention if several slaves started transmitting different data. All addresses of the format 1111 xxx should be reserved for future purposes. 8042D–AVR–10/11 START STOP START ATmega16HVB/32HVB REPEATED START STOP 155 ...
Page 156
... Master consequence, the Slave can reduce the TWI data transfer speed by prolonging the SCL duty cycle. Figure 27-6 on page 157 transmitted between the SLA+R/W and the STOP condition, depending on the software protocol implemented by the application software. ATmega16HVB/32HVB 156 Addr MSB SDA SCL ...
Page 157
... SCL bus 8042D–AVR–10/11 Addr MSB Addr LSB R/W ACK START SLA+R/W TA low Line TB low Masters Start Counting Low Period ATmega16HVB/32HVB Data MSB Data LSB Data Byte TA high TB high Masters Start Counting High Period ACK 9 STOP 157 ...
Page 158
... This implies that in multi-master systems, all data transfers must use the same composi- tion of SLA+R/W and data packets. In other words: All transmissions must contain the same number of data packets, otherwise the result of the arbitration is undefined. ATmega16HVB/32HVB 158 START Master A Loses Arbitration, SDA A SDA 8042D– ...
Page 159
... Bus Interface Unit START / STOP Spike Suppression Control Address/Data Shift Arbitration Detection Register (TWDR) Address Match Unit Address Register (TWAR) Address Comparator ATmega16HVB/32HVB Figure 27-9. The shaded reg- Spike Filter Bit Rate Generator Prescaler Bit Rate Register Ack (TWBR) Control Unit Status Register ...
Page 160
... The TWI may or may not acknowledge its address, depending on settings in the TWCR. The Address Match unit is able to compare addresses even when the AVR MCU is in sleep mode, enabling the MCU to wake-up if addressed by a Master. ATmega16HVB/32HVB 160 SCL frequency The TWI clock is synchronous to the CPU. ...
Page 161
... After the TWI has been addressed by own slave address or general call • After the TWI has received a data byte • After a STOP or REPEATED START has been received while still addressed as a Slave • When a bus error has occurred due to an illegal START or STOP condition 8042D–AVR–10/11 ATmega16HVB/32HVB 161 ...
Page 162
... START condition was successfully transmitted. If TWSR indicates otherwise, the applica- tion software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must load SLA+W into TWDR. Remember ATmega16HVB/32HVB 162 is a simple example of how the application can interface to the TWI hardware ...
Page 163
... TWINT clears the flag. The TWI will then commence executing whatever operation was specified by the TWCR setting In the following an assembly and C implementation of the example is given. Note that the code below assumes that several definitions have been made for example by using include-files. 8042D–AVR–10/11 ATmega16HVB/32HVB 163 ...
Page 164
... MT_DATA_ACK brne ERROR 7 ldi r16, (1<<TWINT)|(1<<TWEN)| (1<<TWSTO) out TWCR, r16 Note: 1. See ”About code examples” on page ATmega16HVB/32HVB 164 (1) C example TWCR = (1<<TWINT)|(1<<TWSTA)| (1<<TWEN) while (!(TWCR & (1<<TWINT))) ; if ((TWSR & 0xF8) != START) ERROR(); TWDR = SLA_W; TWCR = (1<<TWINT) | (1<<TWEN); ...
Page 165
... Master Receiver mode entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered. All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. 8042D–AVR–10/11 ATmega16HVB/32HVB START condition REPEATED START condition Read bit (high level at SDA) ...
Page 166
... TWCR Value This scheme is repeated until the last byte has been sent and the transfer is ended by generat- ing a STOP condition or a repeated START condition. A STOP condition is generated by writing the following value to TWCR: TWCR Value ATmega16HVB/32HVB 166 Device 1 Device 2 Device 3 MASTER SLAVE ...
Page 167
... No TWDR action TWDR action TWDR action ATmega16HVB/32HVB TWWC TWEN – TWEA Next action taken by TWI hardware X SLA+W will be transmitted; ACK or NOT ACK will be received X SLA+W will be transmitted; ACK or NOT ACK will be received X SLA+R will be transmitted ...
Page 168
... Next transfer started with a repeated start condition Not acknowledge received after the slave address Not acknowledge received after a data byte Arbitration lost in slave address or data byte Arbitration lost and addressed as slave ATmega16HVB/32HVB 168 MT S SLA W A DATA $08 $ $20 Other master ...
Page 169
... Device 3 MASTER SLAVE RECEIVER TRANSMITTER TWINT TWEA TWSTA TWINT TWEA TWSTA Table 27-12 on page 168. Received data can be read from the TWDR Register ATmega16HVB/32HVB V BUS ........ Device n R1 TWSTO TWWC TWEN Table 27-2 on page 167). In order to enter MR mode, TWSTO TWWC TWEN 0 X ...
Page 170
... ACK has been received 0x48 SLA+R has been transmitted; NOT ACK has been received 0x50 Data byte has been received; ACK has been returned 0x58 Data byte has been received; NOT ACK has been returned ATmega16HVB/32HVB 170 TWINT TWEA TWSTA TWSTO TWINT ...
Page 171
... A continues $68 $78 DATA From master to slave From slave to master n 27-15). All the status codes mentioned in this section assume that the prescaler bits are Device 1 Device 2 Device 3 SLAVE MASTER RECEIVER TRANSMITTER ATmega16HVB/32HVB DATA A DATA A P $50 $ $10 P Other master A continues $38 To corresponding ...
Page 172
... Observe that if the AVR is set up with a long start-up time, the SCL line may be held low for a long time, blocking other data transmissions. Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these Sleep modes. ATmega16HVB/32HVB 172 TWA6 TWA5 ...
Page 173
... Read data byte Read data byte ATmega16HVB/32HVB TWEA Next action taken by TWI hardware 0 Data byte will be received and NOT ACK will be returned 1 Data byte will be received and ACK will be returned 0 Data byte will be received and NOT ACK will be ...
Page 174
... Last data byte received is not acknowledged Arbitration lost as master and addressed as slave Reception of the general call address and one or more data bytes Last data byte received is not acknowledged Arbitration lost as master and addressed as slave by general call ATmega16HVB/32HVB 174 S SLA W A $60 A $68 General Call A ...
Page 175
... All the status codes mentioned in this section assume that the prescaler bits are Device 1 Device 2 Device 3 SLAVE MASTER TRANSMITTER RECEIVER TWA6 TWA5 TWA4 Device’s Own Slave Address TWINT TWEA TWSTA ATmega16HVB/32HVB V BUS ........ R1 R2 Device n TWA3 TWA2 TWA1 TWA0 TWSTO TWWC TWEN – ...
Page 176
... Data byte in TWDR has been transmitted; NOT ACK has been received 0xC8 Last data byte in TWDR has been transmitted (TWEA = “0”); ACK has been received ATmega16HVB/32HVB 176 Application software response To TWCR To/from TWDR STA STO TWINT Load data byte or ...
Page 177
... From master to slave From slave to master n Application software response To TWCR STA STO TWINT To/from TWDR No TWDR action No TWCR action No TWDR action ATmega16HVB/32HVB DATA A DATA $B8 $C0 A All 1's $C8 Any number of data bytes A and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the Two-wire Serial Bus ...
Page 178
... Two or more masters are accessing the same slave with different data or direction bit. In this case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters trying ATmega16HVB/32HVB 178 Master Transmitter ...
Page 179
... Once the bus is discon- nected, the TWBCIP bit should be cleared. This enables detection of when the bus is connected, and prevents repetitive interrupts if the SCL and SDA lines remain low. 8042D–AVR–10/11 ATmega16HVB/32HVB Figure 27-21. Possible status values are given in circles. SLA ...
Page 180
... Figure 27-22. Overview of bus connect/disconnect. SDA ATmega16HVB/32HVB 180 SCL TWBCIP DELAY ELEMENT START OUTPUT DELAY SET TWBCIF TWBCSR 8-BIT DATA BUS IRQ 8042D–AVR–10/11 ...
Page 181
... TWBR7 TWBR6 TWBR5 TWBR4 R/W R/W R/W R for calculating bit rates TWINT TWEA TWSTA TWSTO R/W R/W R/W R ATmega16HVB/32HVB TWBR3 TWBR2 TWBR1 TWBR0 R/W R/W R/W R ”Bit rate generator TWWC TWEN – TWIE R R ...
Page 182
... This approach is used in this datasheet, unless otherwise noted. • Bit 2 – Reserved This bit is reserved and will always read as zero. • Bits 1:0 – TWPS: TWI Prescaler Bits These bits can be read and written, and control the bit rate prescaler. ATmega16HVB/32HVB 182 ...
Page 183
... TWD7 TWD6 TWD5 R/W R/W R TWA6 TWA5 TWA4 R/W R/W R ATmega16HVB/32HVB Prescaler value 160. The value of TWPS1:0 is used TWD4 TWD3 TWD2 TWD1 R/W R/W R/W R TWA3 TWA2 ...
Page 184
... TWAR. detail. Figure 27-23. TWI Address Match Logic, Block Diagram. • Bit 0 – Reserved This bit is an unused in the Atmel ATmega16HVB/32HVB, and will always read as zero. 27.10.7 TWBCSR – TWI Bus Control and Status Register Bit (0xBE) ...
Page 185
... Connect/Disconnect occurs, that is, when the TWBCIE bit is set. • Bit 5:3 – Reserved These bits are reserved in the Atmel ATmega16HVB/32HVB and will always read as zero. • Bit 2:1 – TWBDT1, TWBDT0: TWI Bus Disconnect Time-out Period The TWBDT bits decides how long both the TWI data (SDA) and clock (SCL) signals must be low before generating the TWI Bus Disconnect Interrupt ...
Page 186
... I/O pin with pull-up enabled and becomes the commu- nication gateway between target and emulator. Figure 28-1. The debugWIRE setup. Figure 28-1 connector. The system clock is not affected by debugWIRE and will always be the clock source selected by the OSCSEL Fuses. ATmega16HVB/32HVB 186 dW dW dW(RESET) dW(RESET) ...
Page 187
... This register is only accessible by the debugWIRE and can therefore not be used as a general purpose register in the normal operations. 8042D–AVR–10/11 will not work CC ® will insert a BREAK instruction in the Program memory. The instruc DWDR[7:0] R/W R/W R/W R ATmega16HVB/32HVB R/W R/W R/W R DWDR 187 ...
Page 188
... BLS since the SPM instruction can initiate a programming when executing from the BLS only. The SPM instruction can access the entire Flash, including the BLS itself. The protection level for the Boot Loader section can be selected by the Boot Loader Lock bits (Boot Lock bits 1), see ATmega16HVB/32HVB 188 (1) size 1 ...
Page 189
... The main difference between the two sections is: ”SPMCSR – Store Program Memory Control and Status Register” on page 202 Read-while-write features. Which section can be read during programming? RWW section NRWW section NRWW section ATmega16HVB/32HVB CPU Read-while-write halted? supported? No None Yes ...
Page 190
... Figure 29-1. Read-while-write vs. no read-while-write. ATmega16HVB/32HVB 190 Read-While-Write (RWW) Section Z-pointer No Read-While-Write Addresses RWW (NRWW) Section Section Code Located in NRWW Section Can be Read During the Operation Z-pointer Addresses NRWW Section CPU is Halted During the Operation 8042D–AVR–10/11 ...
Page 191
... Application Flash Section End Application Start Boot Loader Boot Loader Flash Section Flashend 1. The parameters in the figure above are given in for further details. The Boot Lock bits can be set in software and in ATmega16HVB/32HVB Program Memory BOOTSZ = '10' 0x0000 Application Flash Section End RWW Start NRWW ...
Page 192
... The content of the Z-pointer is ignored and will have no effect on the operation. The LPM instruction does also use the Z-pointer to store the address. Since this instruction addresses the Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used. ATmega16HVB/32HVB 192 (1) Boot Reset Fuse ...
Page 193
... PROGRAM PCPAGE COUNTER PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PAGE 1. The different variables used in Figure 29 page 201. ”Simple assembly code example for a boot loader” on page 198 ATmega16HVB/32HVB (1) . ZPAGEMSB PAGEMSB PCWORD WORD ADDRESS WITHIN A PAGE PAGE INSTRUCTION WORD ...
Page 194
... RWW section after the programming is completed, the user software must clear the RWWSB by writing the RWWSRE. See page 198 ATmega16HVB/32HVB 194 ”Interrupts” on page 52, or the interrupts must be disabled. Before addressing ”Simple assembly code example for a boot loader” on for an example. ” ...
Page 195
... FLB5 Table 30-3 on page 205 for detailed description and mapping of the Fuse High byte FHB7 FHB6 FHB5 Table 29-3 on page 196 and set the SIGRD and SPMEN bits in SPMCSR. When an ATmega16HVB/32HVB BLB11 BLB02 BLB01 LB2 bits). For future compatibility Set” ...
Page 196
... V-ADC Cell3 gain calibration word L V-ADC Cell3 gain calibration word H V-ADC Cell4 gain calibration word L V-ADC Cell4 gain calibration word H V-ADC Cell1 offset V-ADC Cell2 offset V-ADC Cell3 offset V-ADC Cell4 offset V-ADC0 gain calibration word L ATmega16HVB/32HVB 196 Manual. Signature row addressing. (1) (2) (3) (4) (5) ...
Page 197
... Calibration word used to compensate for gain error in ADC1. 14. Calibration byte used to compensate for offset in ADC0 and ADC1. 15. Hot temperature used for factory calibration in °C. 16. Atmel does not test that the combination of lot ID and position is unique. ATmega16HVB/32HVB Z-pointer address 27H 28H 29H ...
Page 198
... Wrloop ; execute Page Write subi ZL, low(PAGESIZEB) sbci ZH, high(PAGESIZEB) ldi call Do_spm ; re-enable the RWW section ldi ATmega16HVB/32HVB 198 (1) SPM Programming Time . Symbol 1. Minimum and maximum programming time is per individual operation. ;PAGESIZEB is page size in BYTES, not words spmcrval, (1<<PGERS) | (1<<SPMEN) spmcrval, (1< ...
Page 199
... PAGESIZEB<=256 ;restore pointer r0, Z+ r1, Y+ Error ;use subi for PAGESIZEB<=256 temp1, SPMCSR ; If RWWSB is set, the RWW section is not ready yet spmcrval, (1<<RWWSRE) | (1<<SPMEN) temp1, SPMCSR temp2, SREG SPMCSR, spmcrval SREG, temp2 ATmega16HVB/32HVB 199 ...
Page 200
... The Atmel ATmega16HVB boot loader parameters In Table 29-5 ming are given Table 29- Note: Table 29-6. Section Read-while-write section (RWW) No read-while-write section (NRWW) Note: Table 29-7. Variable PCMSB PAGEMSB ZPCMSB ZPAGEMSB PCPAGE PCWORD Note: ATmega16HVB/32HVB 200 through Table 29-7, the parameters used in the description of the Self-Program- ...