ATmega16HVB Atmel Corporation, ATmega16HVB Datasheet - Page 63

• Manufacturer Part Number: ATmega16HVB
• Manufacturer: Atmel Corporation

Specifications of ATmega16HVB

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 8 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 17
• Ext Interrupts: 15
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 4.0 to 25
• Operating Voltage (vcc): 4.0 to 25
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

14.2
14.2.1
14.2.2
8042D–AVR–10/11
High voltage ports as general digital I/O
Configuring the pin
Reading the pin
The high voltage ports are high voltage tolerant open collector output ports. In addition they can
be used as general digital inputs.
pin, here generically called Pxn.
Figure 14-2. General high voltage digital I/O
Notes:
Each port pin consist of two register bits: PORTxn and PINxn. As shown in
on page
PINx I/O address.
If PORTxn is written logic one, the port pin is driven low (zero). If PORTxn is written logic zero,
the port pin is tri-stated. The port pins are tri-stated when a reset condition becomes active, even
if no clocks are running.
The port pin can be read through the PINxn Register bit. As shown in
Register bit and the preceding latch constitute a synchronizer. This is needed to avoid metasta-
bility if the physical pin changes value near the edge of the internal clock, but it also introduces a
delay.
1. WRx, RRx and RPx are common to all pins within the same port. clk
2. The High Voltage Digital Input is not present on PC5.
66, the PORTxn bits are accesed at the PORTx I/O address, and the PINxn bits at the
mon to all ports.
Pxn
SLEEP:
clkI/O:
HIGH VOLTAGE DIGITAL INPUT
SLEEP CONTROL
I/O CLOCK
Figure 14-2
SLEEP
(2)
(1)
shows a functional description of one output port
.
SYNCHRONIZER
RRx:
WRx:
RPx:
ATmega16HVB/32HVB
D
L
RESET
CLR
SET
PORTxn
Q
Q
_
CLR
Q
_
Q
READ PORTx REGISTER
WRITE PORTx REGISTER
READ PINx REGISTER
D
D
PINxn
CLR
Q
_
Q
RRx
WRx
clk
RPx
Figure
I/O
I/O
”Register description”
and SLEEP are com-
14-2, the PINxn
63