ATmega16HVB Atmel Corporation, ATmega16HVB Datasheet - Page 146

• Manufacturer Part Number: ATmega16HVB
• Manufacturer: Atmel Corporation

Specifications of ATmega16HVB

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 8 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 17
• Ext Interrupts: 15
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 4.0 to 25
• Operating Voltage (vcc): 4.0 to 25
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

25.3
25.3.1
146
Operation and usage
ATmega16HVB/32HVB
Normal operation
For safe operation the FET driver automatically turns off both the Charge and Discharge FET if
the autonomous Battery Protection circuitry (see
illegal current condition. If such conditions occur, software is not allowed to turn on the FETs
until the current condition has normalized.
To charge deeply discharged cells the ATmega16HVB/32HVB can be configured to run in Deep
Under Voltage Recovery (DUVR) mode. Using chargers with pre-charge current functionality,
this allows charging of deeply discharge cells without an additional pre-charge FET. For char-
gers without a pre-charge limitation current, an optional pre-charge FET in parallel with a charge
FET is supported to be able to charge deeply discharge cells.
In normal operation (DUVRD=1), the FET control is used to enable and disable the Charge FET
and Discharge FET. Normally, the FETs are enabled and disabled by SW writing to the FET
Control and Status Register (FCSR). However, the autonomous Battery Protection circuitry will if
necessary override SW settings to protect the battery cells from too high Charge- or Discharge
currents. Note that the CPU is never allowed to enable a FET that is disabled by the battery pro-
tection circuitry. The FET control is shown in
Figure 25-2. FET control module.
If Current Protection is activated by the Battery Protection circuitry both the Charge-FET and
Discharge FET will be disabled by hardware. When the protection condition disappears the Cur-
rent Protection Timer will ensure a hold-off time of 1 second before software can re-enable the
external FETs.
To turn on the Charge and Discharge FET a minimum VFET supply voltage is required. When
the C-FET/D-FET is off with a total cell voltage lower than 6V, SW should not turn on the C-
FET/D-FET unless a charger is connected. If the total cell voltage is higher than 6V, it is safe for
SW to turn on C-FET or D-FET. Note however, if the FETs are already turned-on, the FET driver
can operate in the entire supply operating range of the device.
The C-FET/D-FETs is switched on by pumping the gate OC/OD above the source voltage
(PVT/BATT) of the external FET. When the gate-source voltage has reached a level higher than
External_Protection_Input
Power-off Mode
CURRENT_PROTECTION
Current Protection
Register
Control
Timer
Status
FET
and
DUVRD
CFE
DFE
Figure 25-1 on page
”Battery protection” on page
145.
DISCHARGE_EN
132) detects an
CHARGE_EN
DUVR_OFF
8042D–AVR–10/11