ATmega16HVB Atmel Corporation, ATmega16HVB Datasheet - Page 151

• Manufacturer Part Number: ATmega16HVB
• Manufacturer: Atmel Corporation

Specifications of ATmega16HVB

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 8 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 17
• Ext Interrupts: 15
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 4.0 to 25
• Operating Voltage (vcc): 4.0 to 25
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

26. Cell balancing
26.1
8042D–AVR–10/11
Overview
The Atmel ATmega16HVB/32HVB incorporates cell balancing FETs. The chip provides one cell
balancing FET for each battery cell in series. The FETs are directly controlled by the application
software, allowing the cell balancing algorithms to be implemented in software. The FETs are
connected in parallel with the individual battery cells. The cell balancing is illustrated in
26-1. The figure shows a four-cell configuration. The cell balancing FETs are disabled in the
Power-off mode.
For typical current through the Cell Balancing FETs, see
The Cell Balancing FETs are controlled by the CBCR. Neighbouring FETs cannot be simultane-
ously enabled. If trying to enable two neighbouring FETs, both will be disabled.
Figure 26-1. Cell balancing.
RP
RP
RP
RP
RP
T
T
T
T
CB
CB
CB
CB
PV4
PV3
PV2
PV1
NV
Level
Shift
Level
Shift
Level
Shift
Level
Shift
ATmega16HVB/32HVB
”Electrical characteristics” on page
Control Register
Cell Balancing
Figure
225.
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