ATmega16HVB Atmel Corporation, ATmega16HVB Datasheet - Page 83

• Manufacturer Part Number: ATmega16HVB
• Manufacturer: Atmel Corporation

Specifications of ATmega16HVB

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 8 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 17
• Ext Interrupts: 15
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 4.0 to 25
• Operating Voltage (vcc): 4.0 to 25
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

17.2.2
17.3
17.4
8042D–AVR–10/11
Timer/Counter clock sources
Counter unit
Definitions
pare Register. OCRnA contains the low byte of the word and OCRnB contains the higher byte of
the word. When accessing 16-bit registers, special procedures described in section
registers in 16-bit mode” on page 90
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the Tn pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment its value. The Timer/Counter is inactive when no clock source is selected. The
output from the Clock Select logic is referred to as the timer clock (clk
Many register and bit references in this section are written in general form. A lower case “n”
replaces the module number, for example Timer/Counter number. A lower case “x” replaces the
unit, for example OCRnx and ICPnx describes OCRnA/B and ICP1/0x . However, when using
the register or bit defines in a program, the precise form must be used, that is, TCNT0L for
accessing Timer/Counter0 counter value and so on.
The definitions in
Table 17-1.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source.
The Clock Select logic is controlled by the Clock Select (CSn2:0) bits located in the Timer/Coun-
ter Control Register n B (TCCRnB), and controls which clock source and edge the
Timer/Counter uses to increment its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clk
details on clock sources and prescaler, see
page
The main part of the 8-bit Timer/Counter is the counter unit.
of the counter and its surroundings.
Figure 17-2. Counter unit block diagram.
BOTTOM
MAX
TOP
79.
DATA BUS
The counter reaches the BOTTOM when it becomes 0
The counter reaches its MAXimum when it becomes 0xFF (decimal 255) in 8-bit mode or
0xFFFF (decimal 65535) in 16-bit mode
The counter reaches the TOP when it becomes equal to the highest value in the count
sequence. The TOP value can be assigned to be the fixed value 0xFF/0xFFFF (MAX) or
the value stored in the OCRnA Register
Definitions.
TCNTn
Table 17-1
are also used extensively throughout the document.
must be followed.
count
”Timer/Counter0 and Timer/Counter1 prescalers” on
Control Logic
top
ATmega16HVB/32HVB
TOVn
(Int.Req.)
clk
Tn
Figure 17-2
Clock Select
( From Prescaler )
Detector
Edge
Tn
).
shows a block diagram
”Accessing
Tn
Tn
). For
83