ATmega16HVB Atmel Corporation, ATmega16HVB Datasheet - Page 195

• Manufacturer Part Number: ATmega16HVB
• Manufacturer: Atmel Corporation

Specifications of ATmega16HVB

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 8 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 17
• Ext Interrupts: 15
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 4.0 to 25
• Operating Voltage (vcc): 4.0 to 25
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

29.8.7
29.8.8
29.8.9
8042D–AVR–10/11
Setting the lock bits by SPM
Reading the fuse and lock bits from software
Reading the signature row from software
To set the Lock bits, write the desired data to R0, write “X0001001” to SPMCSR and execute
SPM within four clock cycles after writing SPMCSR.
See
access.
If bits 5:0 in R0 are cleared (zero), the corresponding Lock bit will be programmed if an SPM
instruction is executed within four cycles after LBSET and SPMEN are set in SPMCSR. The Z-
pointer is don’t care during this operation, but for future compatibility it is recommended to load
the Z-pointer with 0x0001 (same as used for reading the lO
also recommended to set bits 7 and 6 in R0 to “1” when writing the Lock bits. When program-
ming the Lock bits the entire Flash can be read during the operation.
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Z-pointer with 0x0001 and set the LBSET and SPMEN bits in SPMCSR. When an LPM instruc-
tion is executed within three CPU cycles after the LBSET and SPMEN bits are set in SPMCSR,
the value of the Lock bits will be loaded in the destination register. The LBSET and SPMEN bits
will auto-clear upon completion of reading the Lock bits. When LBSET and SPMEN are cleared,
LPM will work as described in the
The algorithm for reading the Fuse Low byte is similar to the one described above for reading
the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the LBSET and
SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles after the
LBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will be
loaded in the destination register as shown below. Refer to
detailed description and mapping of the Fuse Low byte.
Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM instruc-
tion is executed within three cycles after the LBSET and SPMEN bits are set in the SPMCSR,
the value of the Fuse High byte (FHB) will be loaded in the destination register as shown below.
Refer to
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are
unprogrammed, will be read as one.
To read the Signature Row from software, load the Z-pointer with the signature byte address
given in
LPM instruction is executed within three CPU cycles after the SIGRD and SPMEN bits are set in
SPMCSR, the signature byte value will be loaded in the destination register. The SIGRD and
SPMEN bits will auto-clear 6 cycles after writing to SPMCSR, which is locked for further writing
Bit
R0
Bit
Rd
Bit
Rd
Bit
Rd
Table 30-2 on page 204
Table 30-3 on page 205
Table 29-3 on page 196
FHB7
FLB7
7
1
7
–
7
7
FHB6
FLB6
6
6
6
1
6
–
for how the different settings of the Lock bits affect the Flash
for detailed description and mapping of the Fuse High byte.
BLB12
”AVR Instruction
BLB12
FLB5
FHB5
and set the SIGRD and SPMEN bits in SPMCSR. When an
5
5
5
5
BLB11
BLB11
FLB4
FHB4
4
4
4
4
Set” description.
BLB02
BLB02
ATmega16HVB/32HVB
FLB3
FHB3
3
3
3
3
ck
BLB01
BLB01
FLB2
FHB2
bits). For future compatibility it is
2
2
2
2
Table 30-4 on page 206
FLB1
FHB1
LB2
LB2
1
1
1
1
FLB0
FHB0
LB1
LB1
0
0
0
0
for a
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