ATmega16HVB Atmel Corporation, ATmega16HVB Datasheet - Page 114

• Manufacturer Part Number: ATmega16HVB
• Manufacturer: Atmel Corporation

Specifications of ATmega16HVB

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 8 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 17
• Ext Interrupts: 15
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 4.0 to 25
• Operating Voltage (vcc): 4.0 to 25
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

19.7.4
19.7.5
19.7.6
114
ATmega16HVB/32HVB
CADICH and CADICL – CC-ADC instantaneous current
CADAC3, CADAC2, CADAC1 and CADAC0 – CC-ADC accumulate current
CADRCC – CC-ADC regular charge current
When a CC-ADC Instantaneous Current conversion is complete, the result is found in these two
registers. CADIC15:0 represents the converted result in 2's complement format. Bits 12:0 are
the 13-bit ADC result (including sign), while bit 15:13 are the sign extension bits.
When CADICL is read, the CC-ADC Instantaneous Current register is not updated until CADCH
is read. Reading the registers in the sequence CADICL, CADICH will ensure that consistent val-
ues are read. When a conversion is completed, both registers must be read before the next
conversion is completed, otherwise data will be lost.
The CADAC3, CADAC2, CADAC1 and CADAC0 Registers contain the Accumulate Current
measurements in 2’s complement format. Bits 17:0 are the 18-bit ADC result (including sign),
while bit 31:18 are the sign extension bits.
When CADAC0 is read, the CC-ADC Accumulate Current register is not updated until CADAC3
is read. Reading the registers in the sequence CADAC0, CADAC1, CADAC2, CADAC3 will
ensure that consistent values are read. When a conversion is completed, all four registers must
be read before the next conversion is completed, otherwise data will be lost.
Bit
(0xE5)
(0xE4)
Bit
Read/Write
Initial Value
Bit
(0xE3)
(0xE2)
(0xE1)
(0xE0)
Read/Write
Initial Value
Bit
(0xE9)
Read/Write
Initial Value
R/W
15
31
23
15
R
R
7
0
0
R
R
R
7
0
0
0
7
0
R/W
14
30
22
14
R
R
6
0
0
R
R
R
6
0
0
0
6
0
R/W
13
29
21
13
R
R
5
0
0
R
R
R
5
0
0
0
5
0
R/W
12
28
20
12
CADAC[31:24]
CADAC[23:16]
R
R
4
0
0
R
R
R
4
CADAC[15:8]
0
0
0
CADIC[15:8]
4
0
CADAC[7:0]
CADIC[7:0]
CADRCC[7:0]
R/W
11
27
19
11
R
R
3
0
0
R
R
R
3
0
0
0
3
0
R/W
10
26
18
10
R
R
R
R
R
2
0
0
2
0
0
0
2
0
R/W
25
17
R
R
R
R
R
9
1
0
0
9
1
0
0
0
1
0
R/W
24
16
R
R
R
R
R
8
0
0
0
8
0
0
0
0
0
0
8042D–AVR–10/11
CADAC3
CADAC2
CADAC1
CADAC0
CADICH
CADICL
CADRCC