ATmega16HVB Atmel Corporation, ATmega16HVB Datasheet - Page 120

• Manufacturer Part Number: ATmega16HVB
• Manufacturer: Atmel Corporation

Specifications of ATmega16HVB

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 8 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 17
• Ext Interrupts: 15
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 4.0 to 25
• Operating Voltage (vcc): 4.0 to 25
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

20.4.3
120
ATmega16HVB/32HVB
VADCL and VADCH – V-ADC Data Register
• Bit 2 – VADSC: Voltage ADC Start Conversion
Write this bit to one to start a new conversion of the selected channel.
VADSC will read as one as long as the conversion is not finished. When the conversion is com-
plete, it returns to zero. Writing zero to this bit has no effect. VADSC will automatically be
cleared when the VADEN bit is written to zero.
• Bit 1 – VADCCIF: V-ADC Conversion Complete Interrupt Flag
This bit is set when a V-ADC conversion completes and the data registers are updated. The V-
ADC Conversion Complete Interrupt is executed if the VADCCIE bit and the I-bit in SREG are
set. VADCCIF is cleared by hardware when executing the corresponding interrupt handling vec-
tor. Alternatively, VADCCIF is cleared by writing a logical one to the flag. Beware that if doing a
Read-Modify-Write on VADCSR, a pending interrupt can be lost.
• Bit 0 – VADCCIE: V-ADC Conversion Complete Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the V-ADC Conversion Complete
Interrupt is activated.
When a V-ADC conversion is complete, the result is found in these two registers. To ensure that
correct data is read, both high and low byte data registers should be read before starting a new
conversion.
• VADC11:0: V-ADC Conversion Result
These bits represent the result from the conversion.
To obtain the best absolute accuracy for the cell voltage measurements, gain and offset com-
pensation is required. Factory calibration values are stored in the device signature row, refer to
section
mV is given by:
The voltage on the ADCn is given by:
Bit
(0x79)
(0x78)
Read/Write
Initial Value
ADCn[mV]
”Reading the signature row from software” on page 195
Cell
n
[mV]
15
R
R
–
7
0
0
=
----- - (VADCH/L VADC ADCn Offset)
10
1
=
⋅
(VADCH/L VADC Cell
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
14
R
R
–
6
0
0
–
–
13
R
R
–
5
0
0
12
n
R
R
–
4
0
0
Offset)
VADC[7:0]
16384
⋅
11
16384
VADC Cell
3
R
R
0
0
⋅
VADC ADCn Gain Calibration Word
10
R
R
2
0
0
n
VADC[11:8]
Gain Calibration Word
for details. The cell voltage in
R
R
9
1
0
0
R
R
8
0
0
0
8042D–AVR–10/11
VADCH
VADCL