ATmega16HVB Atmel Corporation, ATmega16HVB Datasheet - Page 84

• Manufacturer Part Number: ATmega16HVB
• Manufacturer: Atmel Corporation

Specifications of ATmega16HVB

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 8 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 17
• Ext Interrupts: 15
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 4.0 to 25
• Operating Voltage (vcc): 4.0 to 25
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

17.5
Table 17-2.
17.5.1
17.5.2
84
Mode
0
1
2
3
4
5
Modes of operation
ATmega16HVB/32HVB
Normal 8-bit mode
Clear timer on Compare Match (CTC) 8-bit mode
ICENn
0
0
0
0
1
1
Modes of operation.
TCWn
0
0
1
1
0
1
Signal description (internal signals):
The counter is incremented at each timer clock (clk
restarts from BOTTOM. The counting sequence is determined by the setting of the WGMn0 bits
located in the Timer/Counter Control Register (TCCRnA). For more details about counting
sequences, see
external or internal clock source, selected by the Clock Select bits (CSn2:0). When no clock
source is selected (CSn2:0 = 0) the timer is stopped. However, the TCNTn value can be
accessed by the CPU, regardless of whether clk
priority over) all counter clear or count operations. The Timer/Counter Overflow Flag (TOVn) is
set when the counter reaches the maximum value and it can be used for generating a CPU
interrupt.
The mode of operation is defined by the Timer/Counter Width (TCWn), Input Capture Enable
(ICENn) and the Waveform Generation Mode (WGMn0) bits in
Control Register A” on page
In the normal mode, the counter (TCNTnL) is incrementing until it overruns when it passes its
maximum 8-bit value (MAX = 0xFF) and then restarts from the bottom (0x00), see
bit settings. The Overflow Flag (TOVn) will be set in the same timer clock cycle as the TCNTnL
becomes zero. The TOVn Flag in this case behaves like a ninth bit, except that it is only set, not
cleared. However, combined with the timer overflow interrupt that automatically clears the TOVn
Flag, the timer resolution can be increased by software. There are no special cases to consider
in the Normal 8-bit mode, a new counter value can be written anytime. The Output Compare Unit
can be used to generate interrupts at some given time.
In Clear Timer on Compare or CTC mode, the OCRnA Register is used to manipulate the coun-
ter resolution, see
WGMn0
count
clk
top
0
1
0
1
0
0
Tn
Timer/counter mode
of operation
Normal 8-bit Mode
8-bit CTC
16-bit Mode
16-bit CTC
8-bit Input Capture
mode
16-bit Input Capture
mode
”Timer/counter timing diagrams” on page
Table 17-2
94.
for bit settings. In CTC mode the counter is cleared to zero when
Increment or decrement TCNTn by one
Timer/Counter clock, referred to as clk
Signalize that TCNTn has reached maximum value
Table 17-2
OCRnB,
OCRnA
0xFFFF
OCRnA
0xFFFF
shows the different Modes of Operation.
0xFF
0xFF
TOP
Tn
is present or not. A CPU write overrides (has
Tn
) until it passes its TOP value and then
89. clk
Update of
Immediate
Immediate
Immediate
Immediate
OCRx at
–
–
”TCCRnA – Timer/Counter n
Tn
Tn
can be generated from an
in the following
TOV flag set on
MAX (0xFFFF)
MAX (0xFFFF)
MAX (0xFFFF)
MAX (0xFF)
MAX (0xFF)
MAX (0xFF)
Table 17-2
8042D–AVR–10/11
for