ATmega324PA Atmel Corporation, ATmega324PA Datasheet - Page 15

• Manufacturer Part Number: ATmega324PA
• Manufacturer: Atmel Corporation

Specifications of ATmega324PA

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7.5.1
7.5.2
7.6
8272C–AVR–06/11
Instruction Execution Timing
SPH and SPL – Stack Pointer High and Stack pointer Low
RAMPZ – Extended Z-pointer Register for ELPM/SPM
Note:
Table 7-2.
For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown
in
Figure 7-4.
The actual number of bits is implementation dependent. Unused bits in an implementation will
always read as zero. For compatibility with future devices, be sure to write these bits to zero.
Note:
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 7-5 on page 16
by the Harvard architecture and the fast-access Register File concept. This is the basic pipelin-
ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions
per cost, functions per clocks, and functions per power-unit.
Bit
0x3E (0x5E)
0x3D (0x5D)
Read/Write
Initial Value
Bit
0x3B (0x5B)
Read/Write
Initial Value
Bit (Individually)
Bit (Z-pointer)
Figure 7-4 on page
1. Initial values respectively for the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P
1. RAMPZ is only valid for ATmega1284/ATmega1284P
ATmega164A/ATmega164PA
ATmega324A/ATmega324PA
ATmega644A/ATmega644PA
ATmega1284/ATmega1284P
ATmega164A/PA/324A/PA/644A/PA/1284/P
Stack Pointer size
The Z-pointer used by ELPM and SPM
RAMPZ7
R/W
R/W
SP7
15
7
0
R
–
7
0
1
23
7
Device
15. Note that LPM is not affected by the RAMPZ setting.
shows the parallel instruction fetches and instruction executions enabled
RAMPZ6
R/W
SP6
R/W
14
6
0
RAMPZ
R
–
6
0
1
RAMPZ5
R/W
SP5
R/W
CPU
5
0
13
R
–
5
0
1
16
0
, directly generated from the selected clock source for the
(1)
RAMPZ4
R/W
SP12
0/0
SP4
R/W
R/W
4
0
12
4
1
(1)
15
7
RAMPZ3
R/W
SP11
0/1
SP3
R/W
R/W
3
0
11
3
1
(1)
ZH
RAMPZ2
R/W
SP10
1/0
2
0
SP2
R/W
R/W
10
Stack Pointer size
2
1
(1)
0
8
SP[10:0]
SP[11:0]
SP[12:0]
SP[13:0]
RAMPZ1
R/W
SP9
SP1
R/W
R/W
1
0
9
1
0
1
7
7
RAMPZ0
R/W
SP8
SP0
R/W
R/W
0
0
8
0
0
1
ZL
RAMPZ
SPH
SPL
0
0
15