ATmega324PA Atmel Corporation, ATmega324PA Datasheet - Page 340

• Manufacturer Part Number: ATmega324PA
• Manufacturer: Atmel Corporation

Specifications of ATmega324PA

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Table 28-16. 2-wire Serial Bus Requirements (Continued)
Notes:
8272C–AVR–06/11
Symbol
t
t
t
t
t
t
t
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
SU;STO
BUF
1. In ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P, this parameter is characterized and not 100% tested.
2. Required only for f
3. Cb = capacitance of one bus line in pF.
4. f
5. This requirement applies to all ATmega32 Two-wire Serial Interface operation. Other devices connected to the Two-wire
6. The actual low period generated by the ATmega32 Two-wire Serial Interface is (1/f
7. The actual low period generated by the ATmega32 Two-wire Serial Interface is (1/f
Serial Bus need only obey the general f
6MHz for the low time requirement to be strictly met at f
will not be strictly met for f
at full speed (400kHz) with other ATmega32 devices, as well as any other device with a proper t
Parameter
Low Period of the SCL Clock
High period of the SCL clock
Set-up time for a repeated START condition
Data hold time
Data setup time
Setup time for STOP condition
Bus free time between a STOP and START
condition
CK
= CPU clock frequency
Figure 28-5. 2-wire Serial Bus Timing
SCL
> 100kHz.
SCL
SDA
SCL
t
SU;STA
> 308kHz when f
ATmega164A/PA/324A/PA/644A/PA/1284/P
SCL
requirement.
t
CK
HD;STA
= 8MHz. Still, ATmega32 devices connected to the bus may communicate
t
t
of
LOW
f
f
SCL
SCL
SCL
f
f
f
f
f
f
f
f
f
f
f
f
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
Condition
= 100kHz.
≤ 100kHz
> 100kHz
t
HIGH
≤ 100kHz
> 100kHz
≤ 100kHz
> 100kHz
≤ 100kHz
> 100kHz
≤ 100kHz
> 100kHz
≤ 100kHz
> 100kHz
≤ 100kHz
> 100kHz
t
HD;DAT
(6)
(7)
t
LOW
t
SU;DAT
SCL
SCL
- 2/f
- 2/f
250
100
Min
4.7
1.3
4.0
0.6
4.7
0.6
4.0
0.6
4.7
1.3
0
0
CK
CK
), thus the low time requirement
), thus f
LOW
CK
acceptance margin.
t
SU;STO
must be greater than
t
r
3.45
Max
0.9
–
–
–
–
–
–
–
–
–
–
–
–
t
BUF
Units
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
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