ATmega324PA Atmel Corporation, ATmega324PA Datasheet - Page 249

• Manufacturer Part Number: ATmega324PA
• Manufacturer: Atmel Corporation

Specifications of ATmega324PA

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

23.5.1
23.6
8272C–AVR–06/11
Changing Channel or Reference Selection
Differential Gain Channels
Table 23-1.
When using differential gain channels, certain aspects of the conversion need to be taken into
consideration. Note that the differential channels should not be used with an AREF < 2V.
Differential conversions are synchronized to the internal clock CK
clock. This synchronization is done automatically by the ADC interface in such a way that the
sample-and-hold occurs at a specific phase of CK
single conversions, and the first free running conversion) when CK
amount of time as a single ended conversion (13 ADC clock cycles from the next prescaled
clock cycle). A conversion initiated by the user when CK
cycles due to the synchronization mechanism. In Free Running mode, a new conversion is initi-
ated immediately after the previous conversion completes, and since CK
all automatically started (i.e., all but the first) free running conversions will take 14 ADC clock
cycles.
The gain stage is optimized for a bandwidth of 4kHz at all gain settings. Higher frequencies may
be subjected to non-linear amplification. An external low-pass filter should be used if the input
signal contains higher frequency components than the gain stage bandwidth. Note that the ADC
clock frequency is independent of the gain stage bandwidth limitation. For example, the ADC
clock period may be 6 µs, allowing a channel to be sampled at 12 kSPS, regardless of the band-
width of this channel.
If differential gain channels are used and conversions are started by Auto Triggering, the ADC
must be switched off between conversions. When Auto Triggering is used, the ADC prescaler is
reset before the conversion is started. Since the gain stage is dependent of a stable ADC clock
prior to the conversion, this conversion will not be valid. By disabling and then re-enabling the
ADC between each conversion (writing ADEN in ADCSRA to “0” then to “1”), only extended con-
versions are performed. The result from the extended conversions will be valid. See
and Conversion Timing” on page 246
The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary
register to which the CPU has random access. This ensures that the channels and reference
selection only takes place at a safe point during the conversion. The channel and reference
selection is continuously updated until a conversion is started. Once the conversion starts, the
channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Con-
tinuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in
ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after
ADSC is written. The user is thus advised not to write new channel or reference selection values
to ADMUX until one ADC clock cycle after ADSC is written.
Condition
First conversion
Normal conversions, single ended
Auto Triggered conversions
Normal conversions, differential
ATmega164A/PA/324A/PA/644A/PA/1284/P
ADC Conversion Time
for timing details.
from Start of Conversion)
Sample & Hold (Cycles
1.5/2.5
14.5
ADC2
1.5
2
. A conversion initiated by the user (i.e., all
ADC2
is high will take 14 ADC clock
ADC2
Conversion Time (Cycles)
ADC2
is low will take the same
ADC2
equal to half the ADC
is high at this time,
13/14
13.5
25
13
”Prescaling
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