ATmega324PA Atmel Corporation, ATmega324PA Datasheet - Page 90

• Manufacturer Part Number: ATmega324PA
• Manufacturer: Atmel Corporation

Specifications of ATmega324PA

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8272C–AVR–06/11
PCINT24, Pin Change Interrupt Source 24: The PD0 pin can serve as an external interrupt
source.
Table 14-13 on page 90
the overriding signals shown in
Table 14-13. Overriding Signals for Alternate Functions PD7:PD4
Table 14-14. Overriding Signals for Alternate Functions in PD3:PD0
Note:
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
1. When enabled, the 2-wire Serial Interface enables Slew-Rate controls on the output pins PD0
and PD1. This is not shown in this table. In addition, spike filters are connected between the
AIO outputs shown in the port figure and the digital logic of the TWI module.
ATmega164A/PA/324A/PA/644A/PA/1284/P
PD3/INT1/TXD1/
PCINT27
TXEN1
0
TXEN1
1
TXEN1
TXD1
INT1 ENABLE
PCINT27 • PCIE3
1
INT1 INPUT
PCINT27 INPUT
–
PD7/OC2A/
PCINT31
0
0
0
0
OC2A ENABLE
OCA2A
PCINT31 • PCIE3
1
PCINT31 INPUT
–
and
Table 14-14 on page 90
Figure 14-5 on page
PD2/INT0/RXD1/
PCINT26
PORTD2 • PUD
RXEN1
0
0
INT2 ENABLE
PCINT26 • PCIE3
1
INT0 INPUT
RXD1
PCINT26 INPUT
–
RXEN1
0
PD6/ICP1/
OC2B/
PCINT30
0
0
0
0
OC2B ENABLE
OC2B
PCINT30 • PCIE3
1
ICP1 INPUT
PCINT30 INPUT
–
78.
relate the alternate functions of Port D to
PD1/TXD0/
PCINT25
TXEN0
0
TXEN0
1
TXEN0
TXD0
PCINT25 • PCIE3
1
PCINT25 INPUT
–
PD5/OC1A/
PCINT29
0
0
0
0
OC1A ENABLE
OC1A
PCINT29 • PCIE3
1
PCINT29 INPUT
–
(1)
PD0/RXD0/
PCINT27
RXEN1
PORTD0 • PUD
RXEN1
0
0
0
PCINT24 • PCIE3
1
RXD0
PCINT24 INPUT
–
PD4/OC1B/XCK1/
PCINT28
0
0
0
0
OC1B ENABLE
OC1B
PCINT28 • PCIE3
1
PCINT28 INPUT
–
90