DSPIC30F2023 Microchip Technology Inc., DSPIC30F2023 Datasheet - Page 105

• Manufacturer Part Number: DSPIC30F2023
• Description: 28/44-pin Dspic30f1010/202x Enhanced Flash Smps 16-bit Digital Signal Controller
• Manufacturer: Microchip Technology Inc.

11.4.1
The PWM period is specified by writing to the PRx reg-
ister. The PWM period can be calculated using
Equation 11-1.
EQUATION 11-1:
PWM frequency is defined as 1/[PWM period].
When the selected TMRx is equal to its respective
period register, PRx, the following four events occur on
the next increment cycle:
• TMRx is cleared.
• The OCx pin is set.
• The PWM duty cycle is latched from OCxRS into
• The corresponding timer interrupt flag is set.
See Figure 11-1 for key PWM period comparisons.
Timer3 is referred to in the figure for clarity.
11.4.2
When control bits OCM<2:0> (OCxCON<2:0>) = 111,
Fault protection is enabled via the OCFLTA pin. If the a
logic ‘0’ is detected on the OCFLTA pin, the output pins
are placed in a high-impedance state. The state
remains until:
• the external Fault condition has been removed
• the PWM mode is reenabled by writing to the
As a result of the Fault condition, the OCxIF interrupt is
asserted, and an interrupt will be generated, if enabled.
Upon detection of the Fault condition, the OCFLTx bit
in the OCxCON register is asserted high. This bit is a
read-only bit and will be cleared once the external Fault
condition has been removed, and the PWM mode is
reenabled by writing the appropriate mode bits,
OCM<2:0> in the OCxCON register.
© 2006 Microchip Technology Inc.
- Exception 1: If PWM duty cycle is 0x0000,
- Exception 2: If duty cycle is greater than PRx,
OCxR.
and
appropriate control bits
the OCx pin will remain low.
the pin will remain high.
PWM period = [(PRx) + 1] • 4 • T
PWM PERIOD
PWM WITH FAULT PROTECTION
INPUT PIN
PWM PERIOD
(TMRx prescale value)
OSC
•
Preliminary
11.5
When the CPU enters the Sleep mode, all internal
clocks are stopped. Therefore, when the CPU enters
the Sleep state, the output compare channel will drive
the pin to the active state that was observed prior to
entering the CPU Sleep state.
For example, if the pin was high when the CPU
entered the Sleep state, the pin will remain high. Like-
wise, if the pin was low when the CPU entered the
Sleep state, the pin will remain low. In either case, the
output compare module will resume operation when
the device wakes up.
11.6
When the CPU enters the Idle mode, the output
compare module can operate with full functionality.
The output compare channel will operate during the
CPU Idle mode if the OCSIDL bit (OCxCON<13>) is at
logic ‘0’ and the selected time base (Timer2 or Timer3)
is enabled and the TSIDL bit of the selected timer is
set to logic ‘0’.
dsPIC30F1010/202X
Output Compare Operation During
CPU Sleep Mode
Output Compare Operation During
CPU Idle Mode
DS70178C-page 103