DSPIC30F2023 Microchip Technology Inc., DSPIC30F2023 Datasheet - Page 128

• Manufacturer Part Number: DSPIC30F2023
• Description: 28/44-pin Dspic30f1010/202x Enhanced Flash Smps 16-bit Digital Signal Controller
• Manufacturer: Microchip Technology Inc.

dsPIC30F1010/202X
12.10 PWM Duty Cycle Comparison
The PWM module has two to four PWM duty cycle
generators. Three to five 16-bit special function regis-
ters are used to specify duty cycle values for the PWM
module:
• MDC (Master Duty Cycle)
• PDC1, ..., PDC4 (Duty Cycle)
Each PWM generator has its own duty cycle register
(PDCx), and there is a Master Duty Cycle (MDC) reg-
ister. The MDC register can be used instead of individ-
ual duty cycle registers. The MDC register enables
multiple PWM generators to share a common duty
cycle register to reduce the CPU overhead required in
updating multiple duty cycle registers. Multi-phase
power converters are an application where the use of
the MDC feature saves valuable processor time.
The value in each duty cycle register determines the
amount of time that the PWM output is in the active
state. The PWM time base counters are 13 bits wide
and increment twice per instruction cycle. The PWM
output is asserted when the timer/counter is less than
or equal to the Most Significant 13 bits of the duty
cycle register value. Each of the duty cycle registers
allows a 16-bit duty cycle to be specified. The Least
Significant 3 bits of the duty cycle registers are sent to
additional logic for further adjustment of the PWM
signal edge.
Figure 12-14 is a block diagram of a duty cycle
comparison unit.
FIGURE 12-14:
The duty cycle values can be updated at any time. The
updated duty cycle values optionally can be held until
the next rollover of the primary time base before
becoming active.
DS70178C-page 126
15
15
0
Units
Compare Logic
PDCx Register
TMRx
MUX
15
DUTY CYCLE
COMPARISON
1
<=
MDC Register
0
0
MDCx select
Clk
PWMx signal
Preliminary
0
12.11 Complementary PWM Outputs
Complementary PWM Output mode provides true and
inverted PWM outputs on the pair of PWM output pins.
The complement PWM signal is generated by inverting
the active PWM signal. Complementary outputs are
normally available with all of the different PWM modes
except Push-Pull PWM and Independent PWM Output
modes.
12.12 Independent PWM Outputs
Independent PWM Output mode simply replicates the
active PWM output signal on both output pins
associated with a PWM generator.
12.13 Duty Cycle Limits
The duty cycle generators are limited to the range of
allowable values. A value of 0x0008 is the minimum
duty cycle value that will produce an output pulse. This
value represents 8.4 nsec at 30 MIPS. This minimum
range limitation is not a problem in a real world appli-
cation because of the slew-rate limitation of the PWM
output buffers, external FET drivers, and the power
transistors. The application control loop requires larger
duty cycle values to achieve minimum transistor on
times.
The maximum duty cycle value is also limited to
0xFFEF.
The user is responsible for limiting the duty cycle
values to the allowable range of 0x0008 to 0xFFEF.
Note:
A duty cycle of 0x0000 will produce a zero
PWM output, and a 0xFFFF duty cycle
value will produce a high on the PWM
output.
© 2006 Microchip Technology Inc.