DSPIC30F2023 Microchip Technology Inc., DSPIC30F2023 Datasheet - Page 147

• Manufacturer Part Number: DSPIC30F2023
• Description: 28/44-pin Dspic30f1010/202x Enhanced Flash Smps 16-bit Digital Signal Controller
• Manufacturer: Microchip Technology Inc.

13.0
of this group of dsPIC30F1010/202X devices. It is not
intended to be a comprehensive reference source. To
complement the information in this data sheet, refer to
the “dsPIC30F Family Reference Manual” (DS70046).
The Serial Peripheral Interface (SPI) module is a syn-
chronous serial interface useful for communicating with
other peripheral or microcontroller devices. These
peripheral devices may be serial EEPROMs, shift regis-
ters, display drivers, ADC, etc. The SPI module is
compatible with SPI and SIOP from Motorola
The SPI module consists of a 16-bit shift register,
SPIxSR (where x = 1 or 2), used for shifting data in and
out, and a buffer register, SPIxBUF. Two control registers,
SPIxCON1 and SPIxCON2, configure the module. The
SPIxSR register is not accessible by user software. A sta-
tus register, SPIxSTAT, indicates various status
conditions.
The serial interface consists of 4 pins: SDIx (serial data
input), SDOx (serial data output), SCKx (shift clock input
or output), and SSx (active-low slave select).
In Master mode operation, SCK is a clock output but in
Slave mode, it is a clock input.
A series of eight (8) or sixteen (16) clock pulses shift out
bits from the SPIxSR to SDOx pin and simultaneously
shift in data from SDIx pin. An interrupt is generated
when the transfer is complete and the corresponding
interrupt flag bit (SPI1IF or SPI2IF) is set. This interrupt
can be disabled through an interrupt enable bit (SPI1IE
or SPI2IE).
The receive operation is double-buffered. When a com-
plete byte is received, it is transferred from SPIxSR to
SPIxBUF.
If the receive buffer is full when new data is being trans-
ferred from SPIxSR to SPIxBUF, the module sets the
SPIROV bit (SPIxSTAT<6>) to indicate an overflow con-
dition. The transfer of the data from SPIxSR to SPIxBUF
is not completed, and the new data is lost. The module
does not respond to transitions on the SCKx pin while
SPIROV (SPIxSTAT<6>) is ‘1’, effectively disabling the
module until SPIxBUF is read by user software.
Transmit writes are also double-buffered. The user soft-
ware writes to SPIxBUF. When the master or slave trans-
fer is completed, the contents of the shift register
(SPIxSR) are moved to the receive buffer. If any transmit
data has been written to the buffer register, the contents
© 2006 Microchip Technology Inc.
Note:
Note:
SERIAL PERIPHERAL
INTERFACE (SPI)
This data sheet summarizes the features
The dsPIC30F101/202X family has only
one SPI. All references to x = 2 are
intended for software compatibility with
other dsPIC DSC devices.
®
.
Preliminary
of the transmit buffer are moved to SPIxSR. The received
data is thus placed in SPIxBUF and the transmit data in
SPIxSR is ready for the next transfer.
To set up the SPI module for the Master mode of
operation:
1.
2.
3.
4.
5.
To set up the SPI module for the Slave mode of operation:
1.
2.
3.
4.
5.
6.
7.
The SPI module generates an interrupt indicating com-
pletion of a byte or word transfer, as well as a separate
interrupt for all SPI error conditions.
Note:
dsPIC30F1010/202X
If using interrupts:
a)
b)
c)
Write the desired settings to the SPIxCON1
register with MSTEN (SPIxCON1<5>) = 1.
Clear the SPIROV bit (SPIxSTAT<6>).
Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
Write the data to be transmitted to the SPIxBUF
register. Transmission (and reception) start as
soon as data is written to the SPIxBUF register.
Clear the SPIxBUF register.
If using interrupts:
a)
b)
c)
Write the desired settings to the SPIxCON1 and
SPIxCON2 registers with MSTEN
(SPIxCON1<5>) = 0.
Clear the SMP bit (SPIxCON1<9>).
If the CKE (SPIxCON1<8>) bit is set, then the
SSEN bit (SPIxCON1<7>) must be set to enable
the SSx pin.
Clear the SPIROV bit (SPIxSTAT<6>).
Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
Clear the SPIxIF bit in the respective IFSn
register.
Set the SPIxIE bit in the respective IECn
register.
Write the SPIxIP bits in the respective IPCn
register to set the interrupt priority.
Clear the SPIxIF bit in the respective IFSn
register.
Set the SPIxIE bit in the respective IECn
register.
Write the SPIxIP bits in the respective IPCn
register to set the interrupt priority.
Both the transmit buffer (SPIxTXB) and
the receive buffer (SPIxRXB) are mapped
to the same register address, SPIxBUF.
Do not perform read-modify-write opera-
tions (such as bit-oriented instructions) on
the SPIxBUF register.
DS70178C-page 145