DSPIC30F2023 Microchip Technology Inc., DSPIC30F2023 Datasheet - Page 49

• Manufacturer Part Number: DSPIC30F2023
• Description: 28/44-pin Dspic30f1010/202x Enhanced Flash Smps 16-bit Digital Signal Controller
• Manufacturer: Microchip Technology Inc.

5.0
The dsPIC30F1010/202X device has up to 35 interrupt
sources and 4 processor exceptions (traps), which
must be arbitrated based on a priority scheme.
The CPU is responsible for reading the Interrupt Vec-
tor Table (IVT) and transferring the address contained
in the interrupt vector to the Program Counter (PC).
The interrupt vector is transferred from the program
data bus into the Program Counter, via a 24-bit wide
multiplexer on the input of the Program Counter.
The Interrupt Vector Table and Alternate Interrupt Vec-
tor Table (AIVT) are placed near the beginning of pro-
gram memory (0x000004). The IVT and AIVT are
shown in Figure 5-1.
The interrupt controller is responsible for pre-
processing the interrupts and processor exceptions,
prior to their being presented to the processor core.
The peripheral interrupts and traps are enabled, priori-
tized and controlled using centralized special function
registers:
• IFS0<15:0>, IFS1<15:0>, IFS2<15:0>
• IEC0<15:0>, IEC1<15:0>, IEC2<15:0>
• IPC0<15:0>... IPC11<7:0>
• IPL<3:0> The current CPU priority level is explic-
• INTCON1<15:0>, INTCON2<15:0>
© 2006 Microchip Technology Inc.
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
All interrupt request flags are maintained in these
three registers. The flags are set by their respec-
tive peripherals or external signals, and they are
cleared via software.
All interrupt enable control bits are maintained in
these three registers. These control bits are used
to individually enable interrupts from the
peripherals or external signals.
The user-assignable priority level associated with
each of these interrupts is held centrally in these
twelve registers.
itly stored in the IPL bits. IPL<3> is present in the
CORCON register, whereas IPL<2:0> are present
in the STATUS Register (SR) in the processor
core.
Global interrupt control functions are derived from
these two registers. INTCON1 contains the con-
trol and status flags for the processor exceptions.
The INTCON2 register controls the external inter-
rupt request signal behavior and the use of the
alternate vector table.
INTERRUPTS
Preliminary
• The INTTREG register contains the associated
All interrupt sources can be user assigned to one of 7
priority levels, 1 through 7, via the IPCx registers.
Each interrupt source is associated with an interrupt
vector, as shown in Figure 5-1. Levels 7 and 1 repre-
sent the highest and lowest maskable priorities,
respectively.
If the NSTDIS bit (INTCON1<15>) is set, nesting of
interrupts is prevented. Thus, if an interrupt is currently
being serviced, processing of a new interrupt is
prevented, even if the new interrupt is of higher priority
than the one currently being serviced.
Certain interrupts have specialized control bits for
features like edge or level triggered interrupts, inter-
rupt-on-change, etc. Control of these features remains
within the peripheral module that generates the
interrupt.
The DISI instruction can be used to disable the
processing of interrupts of priorities 6 and lower for a
certain number of instructions, during which the DISI bit
(INTCON2<14>) remains set.
When an interrupt is serviced, the PC is loaded with the
address stored in the vector location in Program Mem-
ory that corresponds to the interrupt. There are 63 dif-
ferent vectors within the IVT (refer to Figure 5-1). These
vectors are contained in locations 0x000004 through
0x0000FE of program memory (refer to Figure 5-1).
These locations contain 24-bit addresses, and, in order
to preserve robustness, an address error trap will take
place should the PC attempt to fetch any of these
words during normal execution. This prevents execu-
tion of random data as a result of accidentally decre-
menting a PC into vector space, accidentally mapping
a data space address into vector space, or the PC roll-
ing over to 0x000000 after reaching the end of imple-
mented program memory space. Execution of a GOTO
instruction to this vector space will also generate an
address error trap.
interrupt vector number and the new CPU inter-
rupt priority level, which are latched into vector
number (VECNUM<6:0>) and Interrupt level
(ILR<3:0>) bit fields in the INTTREG register. The
new interrupt priority level is the priority of the
pending interrupt.
Note:
Note:
Note:
dsPIC30F1010/202X
Interrupt flag bits get set when an Interrupt
condition occurs, regardless of the state of
its corresponding enable bit. User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
Assigning a priority level of 0 to an inter-
rupt source is equivalent to disabling that
interrupt.
The IPL bits become read-only whenever
the NSTDIS bit has been set to ‘1’.
DS70178C-page 47