DSPIC30F2023 Microchip Technology Inc., DSPIC30F2023 Datasheet - Page 168

• Manufacturer Part Number: DSPIC30F2023
• Description: 28/44-pin Dspic30f1010/202x Enhanced Flash Smps 16-bit Digital Signal Controller
• Manufacturer: Microchip Technology Inc.

dsPIC30F1010/202X
REGISTER 15-2:
DS70178C-page 166
bit 15
bit 7
Legend: U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
bit 15, 13
bit 14
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7-6
bit 5
URXISEL1
UTXISEL1
R/W-0
R/W-0
UTXISEL1:UTXISEL0: Transmission Interrupt Mode Selection bits
11 =Reserved; do not use
10 =Interrupt when a character is transferred to the Transmit Shift Register and as a result, the
01 =Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
00 =Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at
UTXINV: IrDA Encoder Transmit Polarity Inversion bit
1 = IrDA encoded U1TX idle state is ‘1’
0 = IrDA encoded U1TX idle state is ‘0’
Unimplemented: Read as ‘0’
UTXBRK: Transmit Break bit
1 = Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
0 = Sync Break transmission disabled or completed
UTXEN: Transmit Enable bit
1 = Transmit enabled, U1TX pin controlled by UART1
0 = Transmit disabled, any pending transmission is aborted and buffer is reset. U1TX pin controlled by
UTXBF: Transmit Buffer Full Status bit (Read-Only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
TRMT: Transmit Shift Register Empty bit (Read-Only)
1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has
0 = Transmit Shift Register is not empty, a transmission is in progress or queued
URXISEL1:URXISEL0: Receive Interrupt Mode Selection bits
11 =Interrupt is set on RSR transfer, making the receive buffer full (i.e., has 4 data characters)
10 =Interrupt is set on RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)
0x =Interrupt is set when any character is received and transferred from the RSR to the receive buffer.
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect.
0 = Address Detect mode disabled
URXISEL0
UTXINV
Note 1: Value of bit only affects the transmit properties of the module when the IrDA encoder is
R/W-0
R/W-0
least one character open in the transmit buffer)
cleared by hardware upon completion
PORT.
completed)
Receive buffer has one or more characters.
transmit buffer becomes empty
operations are completed
U1STA: UART1 STATUS AND CONTROL REGISTER
(1)
enabled (IREN = 1).
W = Writable bit
‘1’ = Bit is set
UTXISEL0
ADDEN
R/W-0
R/W-0
RIDLE
R/W-0
U-0
—
Preliminary
HS =Hardware Set
‘0’ = Bit is cleared
UTXBRK
R/W-0
R/W-0
PERR
(1)
UTXEN
R/W-0
R/W-0
FERR
© 2006 Microchip Technology Inc.
HC = Hardware Cleared
x = Bit is unknown
UTXBF
R/W-0
R/W-0
OERR
URXDA
R/W-0
TRMT
R/W-0
bit 8
bit 0