DSPIC30F2023 Microchip Technology Inc., DSPIC30F2023 Datasheet - Page 31

• Manufacturer Part Number: DSPIC30F2023
• Description: 28/44-pin Dspic30f1010/202x Enhanced Flash Smps 16-bit Digital Signal Controller
• Manufacturer: Microchip Technology Inc.

3.0
3.1
The program address space is 4M instruction words. It
is addressable by a 24-bit value from either the 23-bit
PC, table instruction Effective Address (EA), or data
space EA, when program space is mapped into data
space, as defined by Table 3-1. Note that the program
space address is incremented by two between succes-
sive program words, in order to provide compatibility
with data space addressing.
User program space access is restricted to the lower
4M instruction word address range (0x000000 to
0x7FFFFE), for all accesses other than TBLRD/TBLWT,
which use TBLPAG<7> to determine user or configura-
tion space access. In Table 3-1, Read/Write instruc-
tions, bit 23 allows access to the Device ID, the User ID
and the Configuration bits. Otherwise, bit 23 is always
clear.
© 2006 Microchip Technology Inc.
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
Note:
MEMORY ORGANIZATION
Program Address Space
The address map shown in Figure 3-1 is
conceptual, and the actual memory con-
figuration may vary across individual
devices depending on available memory.
Preliminary
FIGURE 3-1:
dsPIC30F1010/202X
Reset –
Reset – Target Address
Alternate Vector Table
Arithmetic Warn. Trap
Device Configuration
Ext. Osc. Fail Trap
Address Error Trap
Stack Error Trap
Program Memory
(4K instructions)
UNITID (32 instr.)
PROGRAM SPACE MEMORY
MAP FOR dsPIC30F1010/
202X
Reserved
User Flash
DEVID (2)
GOTO
Reserved
Reserved
Reserved
(Read 0’s)
Vector 52
Vector 53
Reserved
Reserved
Registers
Vector 0
Vector 1
Reserved
Reserved
Instruction
DS70178C-page 29
000000
000002
000004
000014
00007E
000080
0000FE
000100
001FFE
002000
7FFFFE
800000
8005BE
8005C0
8005FE
800600
F7FFFE
F80000
F8000E
F80010
FEFFFE
FF0000
FFFFFE
Vector Tables