DSPIC30F2023 Microchip Technology Inc., DSPIC30F2023 Datasheet - Page 136

• Manufacturer Part Number: DSPIC30F2023
• Description: 28/44-pin Dspic30f1010/202x Enhanced Flash Smps 16-bit Digital Signal Controller
• Manufacturer: Microchip Technology Inc.

dsPIC30F1010/202X
12.24 PWM Current-Limit Pins
Each PWM generator can select its own current-limit
input source from up to12 current-limit/Fault pins. In the
FCLCONx registers, each PWM generator has control
bits (CLSRC<3:0>) that specify the source for its cur-
rent-limit input signal. Additionally, each PWM genera-
tor has a CLIEN bit in the PWMCONx register that
enables the generation of current-limit interrupt
requests. Each PWM generator has an associated
Fault polarity bit CLPOL in the FCLCONx register.
Figure 12-21 is a diagram of the PWM Current-Limit
control logic.
The current-limit pins actually serve two different pur-
poses. They can be used to implement either Current-
Limit PWM mode or Current Reset PWM mode.
1.
2.
FIGURE 12-21:
DS70178C-page 134
CMP1x
CMP2x
CMP3x
CMP4x
SFLT1
SFLT2
SFLT3
SFLT4
IFLT2
IFLT4
When the CLIEN bit is set in the PWMCONx
registers, the PWMxH,L outputs are forced to
the values specified by the CLDAT<1:0> bits in
the IOCONx register, if the selected current-limit
input signal is asserted.
When the CLMOD bit is zero AND the XPRES
bit in the PWMCONx register is ‘01’ AND the
PWM generator is in Independent Time Base
mode (ITB = 1), then a current-limit signal
resets the time base for the affected PWM gen-
erator. This behavior is called Current Reset
mode, which is used in some Power Factor
Correction (PFC) applications.
Analog Comparator
Module
PWM CURRENT-LIMIT CONTROL LOGIC DIAGRAM
Independent Fault # 2
Independent Fault # 4
Analog Comparator 1
Analog Comparator 2
Analog Comparator 3
Analog Comparator 4
Shared Fault # 1
Shared Fault # 3
Shared Fault # 2
Shared Fault # 4
Generator
PWMx
PWM Period
CLMOD
Reset
‘0000’
‘0001’
‘0010’
‘0011’
‘1000’
‘1001’
‘1010’
‘1011’
‘1101’
‘1111’
EN
CLSRC<3:0>
Preliminary
MUX
XPRES
EN
12.24.1
The state of the PWM current-limit conditions is avail-
able on the CLSTAT bits in the PWMCONx registers.
The CLSTAT bits display the current-limit IRQ flag if
the CLIEN bit is set. If current-limit interrupts are not
enabled, then the CLSTAT bits display the status of the
selected current-limit inputs in positive logic format.
When the current-limit input pin associated with a
PWM generator is not used, these pins become
general purpose I/O or interrupt input pins.
The current-limit pins are normally active high. If set to
‘1’, the CLPOL bit in FCLCONx registers inverts the
selected current-limit input signal to active high.
The interrupts generated by the selected current-limit
signals are combined to create a single interrupt
request signal to the interrupt controller, which has its
own interrupt vector, interrupt flag bit, interrupt enable
bit and interrupt priority bits associated with it.
The Fault pins are also readable through the PORT I/O
logic when the PWM module is enabled. This allows
the user to poll the state of the Fault pins in software.
PWMxH,L
CLDAT<1:0>
Signals
CURRENT-LIMIT INTERRUPTS
2
2
0
1
© 2006 Microchip Technology Inc.
MUX
CLSTAT
2
PWMxH,L