DSPIC30F2023 Microchip Technology Inc., DSPIC30F2023 Datasheet - Page 155

• Manufacturer Part Number: DSPIC30F2023
• Description: 28/44-pin Dspic30f1010/202x Enhanced Flash Smps 16-bit Digital Signal Controller
• Manufacturer: Microchip Technology Inc.

14.0
The Inter-Integrated Circuit (I
complete hardware support for both Slave and Multi-
Master modes of the I
standard, with a 16-bit interface.
This module offers the following key features:
• I
• I
• I
• I
• Serial clock synchronization for I
• I
FIGURE 14-1:
14.1.3
I2CCON and I2CSTAT are Control and Status regis-
ters, respectively. The I2CCON register is readable and
writable. The lower 6 bits of I2CSTAT are read-only.
The remaining bits of the I2CSTAT are read/write.
I2CRSR is the shift register used for shifting data,
whereas I2CRCV is the buffer register to which data
bytes are written, or from which data bytes are read.
I2CRCV is the receive buffer, as shown in Figure 16-1.
I2CTRN is the transmit register to which bytes are writ-
ten during a transmit operation, as shown in Figure 16-2.
© 2006 Microchip Technology Inc.
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046).
operation.
master and slaves.
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control).
collision and will arbitrate accordingly.
2
2
2
2
2
C interface supporting both Master and Slave
C Slave mode supports 7 and 10-bit address
C Master mode supports 7 and 10-bit address
C port allows bidirectional transfers between
C supports Multi-Master operation; detects bus
I
2
C™ MODULE
I
2
C REGISTERS
PROGRAMMER’S MODEL
bit 15
bit 15
2
C serial communication
2
C) module provides
2
C port can be
bit 9
bit 8
bit 7
bit 7
Preliminary
14.1
The hardware fully implements all the master and slave
functions of the I
specifications, as well as 7 and 10-bit addressing.
Thus, the I
a master on an I
14.1.1
The following types of I
• I
• I
See the I
14.1.2
I
is data.
The I2CADD register holds the slave address. A status
bit, ADD10, indicates 10-bit Address mode. The
I2CBRG acts as the Baud Rate Generator (BRG)
reload value.
In receive operations, I2CRSR and I2CRCV together
form a double-buffered receiver. When I2CRSR
receives a complete byte, it is transferred to I2CRCV
and
transmission, the I2CTRN is not double-buffered.
2
C has a 2-pin interface; pin SCL is clock and pin SDA
Note:
dsPIC30F1010/202X
2
2
C Slave operation with 7 or 10-bit address
C Master operation with 7 or 10-bit address
an
Operating Function Description
2
C programmer’s model in Figure 14-1.
2
bit 0
bit 0
bit 0
bit 0
bit 0
bit 0
interrupt
C module can operate either as a slave or
VARIOUS I
PIN CONFIGURATION IN I
Following a Restart condition in 10-bit
mode, the user only needs to match the
first 7-bit address.
2
2
C bus.
C Standard and Fast mode
I2CRCV (8 bits)
I2CTRN (8 bits)
I2CBRG (9 bits)
I2CCON (16 bits)
I2CSTAT (16 bits)
I2CADD (10 bits)
pulse
2
C operation are supported:
2
C MODES
is
generated.
DS70178C-page 153
2
C MODE
During