DSPIC30F2023 Microchip Technology Inc., DSPIC30F2023 Datasheet - Page 133

• Manufacturer Part Number: DSPIC30F2023
• Description: 28/44-pin Dspic30f1010/202x Enhanced Flash Smps 16-bit Digital Signal Controller
• Manufacturer: Microchip Technology Inc.

FIGURE 12-19:
12.19 PWM Interrupts
The PWM module can generate interrupts based on
internal timing or based on external signals via the cur-
rent-limit and Fault inputs. The primary time base mod-
ule can generate an interrupt request when a special
event occurs. Each PWM generator module has its
own interrupt request signal to the interrupt controller.
The interrupt for each PWM generator is an OR of the
trigger event interrupt request, the current-limit input
event or the Fault input event for that module.
There are four interrupt request signals to the interrupt
control plus another interrupt request from the primary
time base on special events.
12.20 PWM Time Base Interrupts
The PWM module can generate interrupts based on
the primary time base and/or the individual time bases
in each PWM generator. The interrupt timing is speci-
fied by the Special Event Comparison Register
(SEVTCMP) for the primary time base, and by the
TRIGx registers for the individual time bases in the
PWM generator modules.
The primary time base special event interrupt is
enabled via the SEIEN bit in the PTCON register. The
individual time base interrupts generated by the trigger
logic in each PWM generator are controlled by the
TRGIEN bit in the PWMCONx registers.
© 2006 Microchip Technology Inc.
PWM TRIGGER BLOCK DIAGRAM
TRIGx Write
Clk
15
15
Compare Logic
TRIGx Register
PTMRx
Preliminary
PDI
PDI
=
12.21 PWM Fault and Current-Limit Pins
The PWM module supports multiple Fault pins for each
PWM generator. These pins are labeled SFLTx
(Shared Fault) or IFLTx (Individual Fault). The Shared
Fault pins can be seen and used by any of the PWM
generators. The Individual Fault pins are usable by
specific PWM generators.
Each PWM generator can have one pin for use as a
cycle-by-cycle current limit, and another pin for use as
either a cycle-by-cycle current limit or a latching current
Fault disable function.
12.22 Leading Edge Blanking
Each PWM generator supports “Leading Edge Blank-
ing” of the current-limit and Fault inputs via the
LEB<9:3> bits and the PHR, PHF, PLR, PLF, FLTLE-
BEN and CLLEBEN bits in the LEBCONx registers.
The purpose of leading edge blanking is to mask the
transients that occur on the application printed circuit
board when the power transistors are turned on and off.
The LEB bits support the blanking (ignoring) of the cur-
rent-limit and Fault inputs for a period of 0 to 1024 nsec
in 8.4 nsec increments following any specified rising or
falling edge of the coarse PWMH and PWML signals.
The coarse PWM signal (signal prior to the PWM fine
tuning) has resolution of 8.4 nsec (at 30 MIPS), which
is the same time resolution as the LEB counters.
The PHR, PHF, PLR and PLF bits select which edge of
the PWMH and PLWL signals will start the blanking
timer. If a new selected edge triggers the LEB timer
while the timer is still active from a previously selected
PWM edge, the timer reinitializes and continues
counting.
3
3
dsPIC30F1010/202X
TRGDIV<2:0>
Divider
Pulse
DS70178C-page 131
PWMx Trigger