DSPIC30F2023 Microchip Technology Inc., DSPIC30F2023 Datasheet - Page 129

• Manufacturer Part Number: DSPIC30F2023
• Description: 28/44-pin Dspic30f1010/202x Enhanced Flash Smps 16-bit Digital Signal Controller
• Manufacturer: Microchip Technology Inc.

12.14 Dead-Time Generation
Dead time refers to a programmable period of time,
specified by the Dead-Time Register (DTR) or the ALT-
DTR register, which prevent a PWM output from being
asserted until its complementary PWM signal has been
deasserted for the specified time. Figure 12-15 shows
the insertion of dead time in a complementary pair of
PWM outputs. Figure 12-16 shows the four dead-time
units that each have their own dead-time value.
Dead-time generation can be provided when any of the
PWM I/O pin pairs are operating in any output mode.
Many power-converter circuits require dead time
because the power transistors cannot switch instanta-
neously. To prevent current “shoot-through” some
amount of time must be provided between the turn-off
event of one PWM output in a complementary pair and
the turn-on event of the other transistor.
The PWM module can also provide negative dead time.
Negative dead time is the forced overlap of the PWMH
and PWML signals. There are certain converter tech-
niques that require a limited amount of
current “shoot-through”.
The dead-time feature can be disabled for each PWM
generator. The dead-time functionality is controlled by
the DTC<1:0> bits in the PWMCON register.
FIGURE 12-15:
© 2006 Microchip Technology Inc.
PWM
Generator #1
Output
PWM1H
PWM1L
Note:
If zero dead time is required, the dead time
feature must be explicitly disabled in the
DTC<1:0> bit in the PWMCON register
DEAD-TIME INSERTION
FOR COMPLEMENTARY
PWM
t
da
t
da
Preliminary
FIGURE 12-16:
12.14.1
Each complementary output pair for the PWM module
has 12-bit down counters to produce the dead-time
insertion. Each dead-time unit has a rising and falling
edge detector connected to the duty cycle comparison
output.
Depending on whether the edge is rising or falling, one
of the transitions on the complementary outputs is
delayed until the associated timer counts down to
zero. A timing diagram indicating the dead-time inser-
tion for one pair of PWM outputs is shown in
Figure 12-15.
12.14.2
The alternate dead time refers to the dead time speci-
fied by the ALTDTR register that is applied to the com-
plementary PWM output. Figure 12-17 shows a dual
dead-time insertion using the ALTDTR register.
dsPIC30F1010/202X
ALTDR1
ALTDTR2
DTR3
DTR1
DTR2
ALTDTR3
DTR4
ALTDTR4
PWM1 in
PWM2 in
PWM3 in
PWM4 in
DEAD-TIME GENERATORS
ALTERNATE DEAD-TIME SOURCE
DEAD-TIME CONTROL
UNITS BLOCK DIAGRAM
Dead-Time Unit
Dead-Time Unit
Dead-Time Unit
Dead-Time Unit
#1
#2
#3
#4
DS70178C-page 127
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
PWM4H
PWM4L