DSPIC30F2023 Microchip Technology Inc., DSPIC30F2023 Datasheet - Page 202

no-image

DSPIC30F2023

Manufacturer Part Number
DSPIC30F2023
Description
28/44-pin Dspic30f1010/202x Enhanced Flash Smps 16-bit Digital Signal Controller
Manufacturer
Microchip Technology Inc.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F2023-20E/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
DSPIC30F2023-20E/PT
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
DSPIC30F2023-20E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F2023-20E/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
DSPIC30F2023-30I/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
DSPIC30F2023-30I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F2023-30I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
DSPIC30F2023-30I/PTD32
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
DSPIC30F2023-30I/PTD32
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F2023T-20E/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
DSPIC30F2023T-30I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
dsPIC30F1010/202X
REGISTER 18-1:
DS70178C-page 200
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LOCK: PLL Lock Status bit (read-only)
1 = Indicates that PLL is in lock
0 = Indicates that PLL is out of lock (or disabled)
This bit is Reset upon:
Reset on POR
Reset when a valid clock switching sequence is initiated by the clock switch state machine
Set when PLL lock is achieved after a PLL start
Reset when lock is lost
Read zero when PLL is not selected as a Group 1 system clock
PRCDEN: Pseudo Random Clock Dither Enable bit
1 = Pseudo random clock dither is enabled
0 = Pseudo random clock dither is disabled
CF: Clock Fail Detect bit (read/clearable by application)
1 = FSCM has detected clock failure
0 = FSCM has NOT detected clock failure
This bit is Reset upon:
Reset on POR
Reset when a valid clock switching sequence is initiated by the clock switch state machine
Set when clock fail detected
TSEQEN: FRC Tune Sequencer Enable bit
1 = The TUN<3:0>, TSEQ1<3:0>,
0 = The TUN<3:0> bits in OSCTUN register tunes the FRC oscillator
Unimplemented: Read as ‘0’
OSWEN: Oscillator Switch Enable bit
1 = Request oscillator switch to selection specified by NOSC<1:0> bits
0 = Oscillator switch is complete
This bit is Reset upon:
Reset on POR
Reset after a successful clock switch
Reset after a redundant clock switch
Reset after FSCM switches the oscillator to (Group 3) FRC
ters sequentially tune the FRC oscillator. Each field being sequentially selected via the
ROLL<2:0> signals from the PWM module.
OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
Preliminary
...
, TSEQ7<3:0> bits in the OSCTUN and the OSCTUN2 regis-
© 2006 Microchip Technology Inc.

Related parts for DSPIC30F2023