DSPIC30F2023 Microchip Technology Inc., DSPIC30F2023 Datasheet - Page 166

• Manufacturer Part Number: DSPIC30F2023
• Description: 28/44-pin Dspic30f1010/202x Enhanced Flash Smps 16-bit Digital Signal Controller
• Manufacturer: Microchip Technology Inc.

dsPIC30F1010/202X
REGISTER 15-1:
DS70178C-page 164
bit 15
bit 7
Legend: U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9-8
bit 7
bit 6
bit 5
bit 4
bit 3
R/W-0 HC
UARTEN
R/W-0
WAKE
UARTEN: UART1 Enable bit
1 = UART1 enabled; all UART1 pins are controlled by UART1 as defined by UEN<1:0>
0 = UART1 disabled; all UART1 pins are controlled by PORT latches; UART1 power consumption minimal
Unimplemented: Read as ‘0’
USIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
IREN: IrDA Encoder and Decoder Enable bit
1 = IrDA encoder and decoder enabled
0 = IrDA encoder and decoder disabled
Unimplemented: Read as ‘0’
ALTIO: UART Alternate I/O Selection bit
1 = UART communicates using U1ATX and U1ARX I/O pins
0 = UART communicates using U1TX and U1RX I/O pins.
Unimplemented: Read as ‘0’
WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit
1 = UART1 will continue to sample the U1RX pin; interrupt generated on falling edge, bit cleared in
0 = No wake-up enabled
LPBACK: UART1 Loopback Mode Select bit
1 = Enable Loopback mode
0 = Loopback mode is disabled
ABAUD: Auto-Baud Enable bit
1 = Enable baud rate measurement on the next character – requires reception of a Sync field (55h);
0 = Baud rate measurement disabled or completed
RXINV: Receive Polarity Inversion bit
1 = U1RX Idle state is ‘0’
0 = U1RX Idle state is ‘1’
BRGH: High Baud Rate Enable bit
1 = BRG generates 4 clocks per bit period (4x Baud Clock, High-Speed mode)
0 = BRG generates 16 clocks per bit period (16x Baud Clock, Standard mode)
LPBACK
Note:
R/W-0
hardware on following rising edge
cleared in hardware upon completion
U-0
—
U1MODE: UART1 MODE REGISTER
This feature is only available for the 16x BRG mode (BRGH = 0).
W = Writable bit
‘1’ = Bit is set
R/W-0 HC
ABAUD
USIDL
R/W-0
RXINV
R/W-0
R/W-0
IREN
Preliminary
HC = Hardware Cleared
‘0’ = Bit is cleared
R/W-0
BRGH
U-0
—
PDSEL1
R/W-0
ALTIO
R/W-0
© 2006 Microchip Technology Inc.
HS = Hardware Select
x = Bit is unknown
PDSEL0
R/W-0
U-0
—
STSEL
R/W-0
U-0
—
bit 8
bit 0