DSPIC30F2023 Microchip Technology Inc., DSPIC30F2023 Datasheet - Page 181

• Manufacturer Part Number: DSPIC30F2023
• Description: 28/44-pin Dspic30f1010/202x Enhanced Flash Smps 16-bit Digital Signal Controller
• Manufacturer: Microchip Technology Inc.

REGISTER 16-7:
© 2006 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
.
bit 15
bit 14
bit 13
bit 12-8
bit 7
bit 6
bit 5
IRQEN5
IRQEN4
R/W-0
R/W-0
IRQEN5: Interrupt Request Enable 5 bit
1 = Enable IRQ generation when requested conversion of channels AN11 and AN10 is completed
0 = IRQ is not generated
PEND5: Pending Conversion Status 5 bit
1 = Conversion of channels AN11 and AN10 is pending. Set when selected trigger is asserted
0 = Conversion is complete
SWTRG5: Software Trigger 5 bit
1 = Start conversion of AN11 and AN10 (if selected by TRGSRC bits). If other conversions are in
progress, then conversion will be performed when the conversion resources are available. This bit will
be reset when the PEND bit is set.
TRGSRC5<4:0>: Trigger Source Selection 5 bits
Selects trigger source for conversion of analog channels A11 and A10.
00000 = No conversion enabled
00001 = Individual software trigger selected
00010 = Global software trigger selected
00011 = PWM Special Event Trigger selected
00100 = PWM generator #1 trigger selected
00101 = PWM generator #2 trigger selected
00110 = PWM generator #3 trigger selected
00111 = PWM generator #4 trigger selected
01100 = Timer #1 period match
01101 = Timer #2 period match
01110 = PWM GEN #1 current-limit ADC trigger
01111 = PWM GEN #2 current-limit ADC trigger
10000 = PWM GEN #3 current-limit ADC trigger
10001 = PWM GEN #4 current-limit ADC trigger
10110 = PWM GEN #1 fault ADC trigger
10111 = PWM GEN #2 fault ADC trigger
11000 = PWM GEN #3 fault ADC trigger
11001 = PWM GEN #4 fault ADC trigger
IRQEN4: Interrupt Request Enable 4 bit
1 = Enable IRQ generation when requested conversion of channels AN9 and AN8 is completed
0 = IRQ is not generated
PEND4: Pending Conversion Status 4 bit
1 = Conversion of channels AN9 and AN8 is pending. Set when selected trigger is asserted.
0 = Conversion is complete
SWTRG4: Software Trigger 4 bit
1 = Start conversion of AN9 and AN8 (if selected by TRGSRC bits). If other conversions are in
progress, then conversion will be performed when the conversion resources are available. This bit will
be reset when the PEND bit is set.
PEND5
PEND4
R/W-0
R/W-0
A/D CONVERT PAIR CONTROL REGISTER #2 (ADCPC2)
W = Writable bit
‘1’ = Bit is set
SWTRG5
SWTRG4
R/W-0
R/W-0
R/W-0
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
R/W-0
dsPIC30F1010/202X
TRGSRC5<4:0>
TRGSRC4<4:0>
R/W-0
R/W-0
x = Bit is unknown
R/W-0
R/W-0
DS70178C-page 179
R/W-0
R/W-0
bit 8
bit 0