MT9074AL Zarlink Semiconductor, Inc., MT9074AL Datasheet - Page 102

• Manufacturer Part Number: MT9074AL
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Zarlink Semiconductor, Inc.

MT9074
102
Bit
7
6
5
4
3
Table 144 - HDLC Control register 1
ADREC
Name
RxEN
TxEN
EOP
FA
(Page B & C, Address 13H)
When high this bit will enable
address
forces the receiver to recognize
only those packets having the
unique address as programmed
in
Recognition Registers or if the
address is an All call address.
When low this bit will disable
the
receiver will disable after the
rest of the packet presently
being received is finished. The
receiver
disabled.
When high the receiver will be
immediately enabled and will
begin searching for flags, Go-
aheads etc.
When low this bit will disable
the
transmitter will disable after the
completion
presently
The transmitter internal clock is
disabled.
When high the transmitter will
be immediately enabled and will
begin transmitting data, if any,
or go to a mark idle or
interframe time fill state.
Forms a tag on the next byte
written the TX FIFO, and when
set will indicate an end of
packet byte to the transmitter,
which will transmit an FCS
following
facilitates loading of multiple
packets into TX FIFO. Reset
automatically after a write to the
TX FIFO occurs.
Forms a tag on the next byte
written to the TX FIFO, and
when set will indicate to the
transmitter that it should abort
the packet in which that byte is
being
automatically after a write to the
TX FIFO.
Functional Description
the
HDLC
HDLC
transmitted.
internal
Receive
being
recognition.
this
of
transmitter.
receiver.
the
byte.
transmitted.
clock
Address
packet
Reset
This
This
The
The
is
Bit
2
1
0
Table 144 - HDLC Control register 1
Mark-Idle
FRUN
Name
TR
(Page B & C, Address 13H)
When low, the transmitter will
be in an idle state. When high it
is in an interframe time fill state.
These two states will only occur
when the TX FIFO is empty.
When high this bit will enable
transparent mode. This will
perform the parallel to serial
conversion without inserting or
deleting zeros. No CRC bytes
are sent or monitored nor are
flags or aborts. A falling edge of
TxEN for transmit and a falling
edge of RxEN for receive is
necessary
transparent mode. This will also
synchronize the data to the
transmit and receive channel
structure. Also, the transmitter
must
control
transparent mode is entered.
When high the HDLC TX and
RX are continuously enabled
providing the RxEN and TxEN
bits are set
Functional Description
be
register
enabled
to
Data Sheet
1
initialize
through
before