MT9074AL Zarlink Semiconductor, Inc., MT9074AL Datasheet - Page 8

• Manufacturer Part Number: MT9074AL
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Zarlink Semiconductor, Inc.

MT9074
8
To accommodate some special applications, the
MT9074 also supports a digital framer only mode by
providing direct access to the transmit and receive
data in digital format, i.e. by-passing the analog LIU
front-end.
The digital portion of the MT9074 connects selected
channels of an incoming stream of time multiplexed
2.048 Mbit/s PCM channels to the transmit payload
of either the T1 or E1 trunk, while the receive
payload is connected to the ST-BUS 2.048 Mbit/s
backplane bus for both data and signaling with
channel times and the frame boundary synchronous
to
conditioning of the line is implemented via a parallel
microprocessor interface.
The MT9074 has a comprehensive suite of status,
alarm,
features. These include counters for BPVs, CRC
errors, F-bit errors (T1 only), E-bit errors (E1 only),
errored frame alignment signals (E1 only), BERT,
OOF (T1 only), and RAI and continuous CRC errors
(E1 only). Also, included are transmission error
insertion for BPVs, CRC-6 errors (T1 only), CRC-4
errors (E1 only), framing bit errors (T1 only), frame
and non-frame alignment signal errors (E1 only),
payload errors and loss of signal errors. A built-in
PRBS generator (2
combination of outgoing channels; an equivalent
PRBS
connected to any combination of receive channels.
A complete set of loopbacks has been implemented,
which include digital, remote, ST-BUS, payload,
local, metallic and remote time slot.
The MT9074 also provides a comprehensive set of
maskable interrupts. Interrupt sources consist of
synchronization
indication and overflow, timer status, slip indication,
maintenance
associated signaling bit changes.
In T1 mode the framer operates in any one of the
framing
Superframe (ESF). The ESF FDL bits of the MT9074
can be accessed either through the data link pins
TxDL, RxDL, RxDLCLK and TxDLCLK, or through
internal registers for Bit Oriented Messages, or
through a built-in HDLC. A second HDLC may be
connected to DS1 channel 24 for the ISDN Primary
Rate signaling applications.
In E1 mode the MT9074 operates in either
termination or transparent modes selectable via
software control. In the termination mode the CRC-4
the
error
performance
transmit
modes:
functions
detector
status,
15
side.
D4,
-1) can be connected to any
monitoring
SLC-96
can
Control,
alarm
and
be
receive
status,
and
and
reporting
independently
Extended
reporting
channel
counter
and
calculation is performed as part of the framing
algorithm. In the transmit transparent mode, no
framing or signaling is imposed on the data transmit
from DSTi on the line. In addition, the MT9074
optionally allows the data link maintenance channel
to be modified and updates the CRC-4 remainder
bits to reflect the modification. All channel, framing
and signaling data passes through the device
unaltered. This is useful for intermediate point
applications of a PCM30 link where the data link data
is modified, but the error information transported by
the CRC-4 bits must be passed to the terminating
end. In the receive transparent mode, the received
line data is channelled to DSTo with framing
operations disabled, consequently, the data passes
through the slip buffer and drives DSTo with an
arbitrary alignment.
In E1 mode the S
MT9074 in the following three ways:
•
•
•
A second HDLC Controller with a 128 byte FIFO is
available for connection to timeslot 16 in E1 mode.
Functional Description
MT9074 Line Interface Unit (LIU)
Receiver
The receiver portion of the MT9074 LIU consists of
an input signal peak detector, an optional equalizer
with two separate high pass sections, a smoothing
filter, data and clock slicers and a clock extractor.
Receive equalization gain can be set manually (i.e.,
software) or it can be determined automatically by
peak detectors.
The output of the receive equalizer is conditioned by
a smoothing filter and is passed on to the clock and
data slicer. The clock slicer output signal drives a
phase locked loop, which generates an extracted
clock (C1.50). This extracted clock is used to sample
the output of the data comparator
In T1 mode, the receiver portion of the LIU can
reliably recover clock and data from signals
attenuated by up to 30 dB @ 772 kHz (translates to
5000 ft. of PIC 24 AWG cable) and tolerate jitter to
the maximum specified by AT&T TR 62411 (see
Figure 3).
In E1 mode the receiver portion of the LIU can
reliably recover clock and data from signals
Programming a register;
Data link pins TxDL, RxDL, RxDLCLK and
TxDLCLK;
HDLC Controller with a 128 byte FIFO.
a
bits can be accessed by the
Data Sheet