MT9074AL Zarlink Semiconductor, Inc., MT9074AL Datasheet - Page 28

• Manufacturer Part Number: MT9074AL
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Zarlink Semiconductor, Inc.

Data Sheet
1
0
The end-of-packet-detect (EOPD) interrupt indicates
that the last byte written to the Rx FIFO was an EOP
byte (last byte in a packet). The end-of-packet-read
(EopR) interrupt indicates that the byte about to be
read from the Rx FIFO is an EOP byte (last byte in a
packet). The Status Register should be read to see if
the packet is good or bad before the byte is read.
A minimum size packet has an 8-bit address, an 8-bit
control byte, and a 16-bit FCS pattern between the
opening and closing flags (see Section 9.3.2). Thus,
the absence of a data transmission error and a frame
length of at least 32 bits results in the receiver writing
a valid packet code with the EOP byte into Rx FIFO.
The last 16 bits before the closing flag are regarded
as the FCS pattern and will not be transferred to the
receiver FIFO. Only data bytes (Address, Control,
Information) are loaded into the Rx FIFO.
In the case of an Rx FIFO overflow, no clocking
occurs until a new opening flag is received. In other
words, the remainder of the packet is not clocked
into the FIFO. Also, the top byte of the FIFO will not
be written over. If the FIFO is read before the
reception of the next packet then reception of that
packet will occur. If two beginning of packet
Write Vectors
188 uS
Read Vectors
Minimum Delay
Read Vectors - Maximum Delay
Read Pointer
221 uS
Read Pointer
129 uS
Pointer
512 Bit
Elastic
Store
Write
0
0
Figure 12 - Read and write pointers in the transmit slip buffers
0 uS
Frame 0
last byte (good packet)
4 uS
Frame 0
Read Pointer
Read Pointer
packet byte
96 uS
62 uS
Frame 1
Frame 1
Frame 0
92 uS
92 uS
conditions (RQ9=0;RQ8=1) are seen in the FIFO,
without an intermediate EOP status, then overflow
occurred for the first packet.
The receiver may be enabled independently of the
transmitter. This is done by setting the RXEN bit of
Control Register 1. Enabling happens immediately
upon writing to the register. Disabling using RXEN
will occur after the present packet has been
completely loaded into the FIFO. Disabling can occur
during a packet if no bytes have been written to the
FIFO yet. Disabling will consist of disabling the
internal receive clock. The FIFO, Status, and
Interrupt Registers may still be read while the
receiver is disabled. Note that the receiver requires a
flag before processing a frame, thus if the receiver is
enabled in the middle of an incoming packet it will
ignore that packet and wait for the next complete
one.
The receive CRC can be monitored in the Rx CRC
Registers. These registers contain the actual CRC
sent by the other transmitter in its original form; that
is, MSB first and bits inverted. These registers are
updated by each end of packet (closing flag)
received and therefore should be read when an end
of packet is received so that the next packet does not
overwrite the registers.
Frame 1
Wander Tolerance
MT9074
28