MT9074AL Zarlink Semiconductor, Inc., MT9074AL Datasheet - Page 22

• Manufacturer Part Number: MT9074AL
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Zarlink Semiconductor, Inc.

MT9074
22
Transmit Data All Ones (TxAO)
Operation
The TxAO (Transmit all ones) pin allows the PRI
interface to transmit an all ones signal from the point
of power-up without writing to any control registers.
During this time the IRQ pin is tristated. After the
interface has been initialized normal operation can
take place by making TxAO high.
Data Link Operation
Data Link Operation in E1 Mode
In E1 mode MT9074 has a user defined 4, 8, 12, 16
or 20 kbit/s data link for transport of maintenance
and performance monitoring information across the
PCM30 link. This channel functions using the S
(S
alignment signal (NFAS). Since the NFAS is
transmitted every other frame - a periodicity of 250
microseconds - the aggregate bit rate is a multiple of
4 kb/s. As there are five S
available for this data link, the bit rate will be 4, 8, 12,
16 or 20 kb/s, depending on the bits selected for the
Data Link (DL).
a4
Transmit MFAS (CAS)
ABCD Bit Debounce
~S
Transmit non-FAS
CRC Interworking
Error Insertion
Transmit Data
Transmit FAS
RxMF Output
a8
Loopbacks
Function
Data Link
Interrupts
Signaling
Counters
) of the PCM30 timeslot zero non-frame
HDLCs
Mode
Table 15 - Reset Status(E1)
Signaling Multiframe
a
CAS Registers
1/S
Deactivated
Deactivated
Deactivated
Deactivated
Deactivated
Termination
bits independently
C
00001111
Activated
All Ones
Masked
Cleared
n
Status
0011011
n
1111111
a
bits
The S
the appropriate bits, S
Select Word (page 01H, address 17H, bits 4-0).
Access to the DL is provided by pins TxDLCLK,
TxDL, RxDLCLK and RxDL, which allow easy
interfacing to an external controller.
Data to be transmit onto the line in the S
is clocked in from the TxDL pad (pin 65 in PLCC, pin
62 in MQFP) with the clock TxDLCLK (pin 64 in
PLCC, pin 61 in MQFP). Although the aggregate
clock rate equals the bit rate, it has a nominal pulse
width of 244 ns, and it clocks in the TxDL as if it were
a 2.048 Mb/s data stream. The clock can only be
active during bit times 4 to 0 of the STBUS frame.
The TxDL input signal is clocked into the MT9074 by
the rising edge of TxDLCLK. If bits are selected to be
a part of the DL, all other programmed functions for
those S
The RxDLCLK signal (pin 39 in PLCC, pin 20 in
MQFP) is derived from the receive extracted clock
and is aligned with the receive data link output RxDL.
The HDB3 decoded receive data, at 2.048 Mbit/s, is
clocked out of the device on pin RxDL (pin 40 in
PLCC, pin 21 in MQFP). In order to facilitate the
attachment of this data stream to a Data Link
controller, the clock signal RxDLCLK consists of
positive pulses, of nominal width of 244 ns, during
the Sa bit cell times that are selected for the data
link. Again, this selection is made by programming
address 17H of master control page 01H. No DL data
will be lost or repeated when a receive frame slip
occurs. See the AC Electrical Characteristics for
timing requirements.
Data Link Operation in T1 Mode
SLC-96 and ESF protocol allow for carrier messages
to be embedded in the overhead bit position. The
MT9074 provides 3 separate means of controlling
these data links. See Data Link and Rx Equalization
Control Word - address 12H, page 1H.
•
•
The data links (transmit and receive) may be
sourced (sunk) from an external controller
using dedicated pins on the MT9074 in T1
mode (enabled by setting the bit 7 - EDL of the
Data link Control Word).
Bit - Oriented Messages may be transmit and
received via a dedicated TxBOM register (page
1H, address 13H) and a RxBOM (page 3H,
address 15H). Transmission is enabled by
setting bit 6 - BIOMEn in the Data link Control
a
a
bits used for the DL are selected by setting
bit positions are overridden.
a4
~S
a8
, to one in the Data Link
Data Sheet
a
bit position