MT9074AL Zarlink Semiconductor, Inc., MT9074AL Datasheet - Page 107

• Manufacturer Part Number: MT9074AL
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Zarlink Semiconductor, Inc.

Data Sheet
7-4
Bit
3
2
1
0
Table 153 - HDLC Test Status Register
VADDR Valid Address. This is the address
RxCLK Receive Clock. This bit represents
TxCLK Transmit Clock. This bit represents
VCRC
Name
RSV
(Page B & C, Address 1CH)
the receiver clock generated after
the RXEN control bit, but before
zero deletion is considered.
the transmit clock generated after
the TXEN control bit, but before
zero insertion is considered.
Valid CRC. This is the CRC
recognition
receiver. Data is clocked into the
register
monitored to see if comparison was
successful (bit will be high).
recognition
receiver. Data is clocked into the
Address Recognition Register and
then this bit is monitored to see if
comparison was successful (bit will
be high).
These bits are reserved.
Functional Description
and
status
status
then
bit
bit
this
for
for
bit
the
the
is
6-4 RFD2-0 These bits select the Rx FIFO full
2-0
Bit
7
3
Table 154 - HDLC Control Register 3
TFD2-0 These bits select the Tx HDLC FIFO
Name
---
---
(Page B & C, Address 1DH)
Unused.
status level:
Unused.
full status level:
RF
D2
TF
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Functional Description
RF
D1
D1
TF
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
RF
D0
D0
TF
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Full Status Level
Full Status Level
MT9074
112
128
112
128
16
32
48
64
80
96
16
32
48
64
80
96
107