MT9074AL Zarlink Semiconductor, Inc., MT9074AL Datasheet - Page 38

• Manufacturer Part Number: MT9074AL
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Zarlink Semiconductor, Inc.

MT9074
38
E-bit Counter (EC9-0)
E-bit errors are counted by the MT9074 in order to
support compliance with ITU-T requirements. This
ten bit counter is located on page 04H, addresses
14H and 15H respectively. It is incremented by single
error events, with a maximum rate of twice per CRC-
4 multiframe.
There are two maskable interrupts associated with
the E-bit error measurement. EBI (page 1, address
1CH) is initiated when the least significant bit of the
counter toggles, and FEBEO (page 01H, address
1DH) is initiated when the counter overflows.
Bipolar Violation Error Counter (BPV15-BPV0)
The bipolar violation error counter will count bipolar
violations or encoding errors that are not part of
HDB3 encoding in E1 mode. This counter BPV15-
BPV0 is 16 bits long (page 4H, addresses 16H and
17H) and is incremented once for every BPV error
received. It should be noted that when presetting or
clearing the BPV error counter, the least significant
BPV counter address should be written to before the
most significant location.
In E1 mode, there are two maskable interrupts
associated
measurement. BPVI (page 01H, address 1CH) is
initiated when the l significant bit of the BPV error
counter toggles. BPVO (page 01H, address 1DH) is
initiated when the counter changes from FFFFH to
0000H.
CRC-4 Error Counter (CC9-0)
CRC-4 errors are counted by the MT9074 in order to
support compliance with ITU-T requirements. This
ten bit counter is located on page 04H, addresses
18H and 19H in E1 mode. It is incremented by single
error events, which is a maximum rate of twice per
CRC-4 multiframe.
There is a maskable interrupt associated with the
CRC error measurement. CRCIM (page 01H,
address 1CH) is initiated when the least significant
bit of the counter toggles, and CRCOM (page 01H,
address
overflows.
PRBS Error Counter (PS7-0)
There are two 8 bit counters associated with PRBS
comparison; one for errors and one for time. Any
errors that are detected in the receive PRBS will
increment the PRBS Error Rate Counter of page
04H, address 10H. Writes to this counter will clear an
8 bit counter, PSM7-0 (page 04H, address 11H)
which counts receive CRC multiframes. A maskable
1DH)
with
is
the
initiated
bipolar
when
violation
the
counter
error
PRBS counter overflow (PRBSO) interrupt (page 1,
address 1DH) is associated with this counter.
CRC Multiframe Counter for PRBS (PSM7-0)
This eight bit counter counts receive CRC-4
multiframes. It can be directly loaded via the
microport. The counter will also be automatically
cleared in the event that the PRBS error counter is
written to by the microport. This counter is located on
page 04H, address 11H.
Error Insertion
In T1 mode, MT9074 has six types of error
conditions can be inserted into the transmit DS1 data
stream through control bits, which are located on
page 1, address 19H - Error Insertion Word. These
error events include the bipolar violation errors
(BPVE), CRC-6 errors (CRCE), Ft errors (FTE), Fs
errors (FSE), payload (PERR) and a loss of signal
condition (LOSE). The LOSE function overrides the
B8ZS encoding function.
In E1 mode, MT9074 has six types of error
conditions can be inserted into the transmit PCM30
data stream through control bits, which are located
on page 01H, address 19H. These error events
include the bipolar violation errors (BPVE), CRC-4
errors (CRCE), FAS errors (FASE), NFAS errors
(NFSE), payload (PERR) and a loss of signal error
(LOSE). The LOSE function overrides the HDB3
encoding function.
Per Time Slot Control Words
There are two per time slot control pages (addresses
AH and BH) (T1/E1) occupying a total of 24 unique
addresses in T1 mode or a total of 32 unique
addresses in E1 mode. Each address controls a
matching timeslot on the 24 DS1 channels (T1) or 32
PCM-30 channels (E1) and the equivalent channel
data on the receive (DSTo) data. For example
address 0 of the first per time slot control page
contains program control for transmit timeslot 0 and
DSTo channel 0.
Per Time Slot Control Word
Bit 7
T1 Mode
E1 Mode
TXMSG ADI
TXMSG PCI
RTSL
RTSL
LTSL
LTSL
TTST
TTST
RRST
RRST
Data Sheet
RPSIG
RPSIG
Bit 0
- - -
CC