MT9074AL Zarlink Semiconductor, Inc., MT9074AL Datasheet - Page 37

• Manufacturer Part Number: MT9074AL
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Zarlink Semiconductor, Inc.

Data Sheet
high - bit 7 of the Interrupt Mask Word One, page 1H,
address 1CH). A counter overflow interrupt may be
enabled by setting control bit FEOM high - bit 2 of
Interrupt Mask Word Two (page 1H, address 1DH).
Out Of Frame / Change Of Frame Alignment
Counter (OOF3-0/COFA3-0)
This register space is shared by two nibbles. One is
the count of out of frame events. The other
independent counter is incremented when, after a
resynchronization, the frame alignment has moved.
This count is reported in page 4, address 13H.
There are two interrupts associated with the Change
of Frame Alignment counter. A single error may
generate an interrupt (enable by setting COFAI high -
bit 4 of the Interrupt Mask Word One, page 1H,
address 1CH). A counter overflow interrupt may be
enabled by setting control bit COFAO high - bit 4 of
Interrupt Mask Word Two (page 1H, address 1DH).
There is one interrupt associated with the Out of
Frame counter. A counter overflow interrupt may be
enabled by setting control bit OOFO high - bit 5 of
Interrupt Mask Word Two (page 1H, address 1DH).
Multiframes out of Sync Counter (MFOOF7-
MFOOF0)
This eight bit counter MFOOF7 - MFOOF0 is located
on page 4 address 15H, and is incremented once per
multiframe (1.5 ms for D4 and 3 ms for ESF) during
the time that the framer is out of terminal frame
synchronization.
There is a maskable interrupt associated with the
measurement. A counter overflow interrupt may be
enabled by setting control bit MFOOFO high - bit 1 of
Interrupt Mask Word Two (page 1H, address 1DH).
CRC-6 Error Counter (CC15-0)
CRC-6 errors are recorded by this counter for ESF
links. This 16 bit counter is located on page 4H,
addresses 18H and 19H.
There are two maskable interrupts associated with
the CRC error measurement. A single error may
generate an interrupt (enable by setting CRCI high -
bit 6 of the Interrupt Mask Word One, page 1H,
address 1CH). A counter overflow interrupt may be
enabled by setting control bit CRCO high - bit 6 of
Interrupt Mask Word Two (page 1H, address 1DH).
Bipolar Violation Error Counter (BPV15-BPV0)
The bipolar violation error counter will count bipolar
violations or encoding errors that are not part of
B8ZS encoding. This counter BPV15-BPV0 is 16 bits
long (page 4H, addresses 16H and 17H) and is
incremented once for every BPV error received. It
should be noted that when presetting or clearing the
BPV error counter, the least significant BPV counter
address should be written to before the most
significant location.
There are two maskable interrupts associated with
the bipolar violation error measurement. A single
error may generate an interrupt (enable by setting
BPVI high - bit 3 of the Interrupt Mask Word One,
page 1H, address 1CH). A counter overflow interrupt
may be enabled by setting control bit BPVO high - bit
3 of Interrupt Mask Word Two (page 1H, address
1DH).
PRBS Error Counter (PS7-0)
There are two 8 bit counters associated with PRBS
comparison; one for errors and one for time. Any
errors that are detected in the receive PRBS will
increment the PRBS Error Rate Counter of page
04H, address 10H. Writes to this counter will clear an
8 bit counter, PSM7-0 (page 01H, address 11H)
which counts receive CRC multiframes. A maskable
PRBS counter overflow (PRBSO) interrupt (page 1,
address 1DH) is associated with this counter.
CRC Multiframe Counter for PRBS (PSM7-0)
This eight bit counter counts receive CRC-4
multiframes. It can be directly loaded via the
microport. The counter will also be automatically
cleared in the event that the PRBS error counter is
written to by the microport. This counter is located on
page 04H, address 11H.
E1 Counters
Errored FAS Counter (EFAS7-EFAS0)
An eight bit Frame Alignment Signal Error counter
EFAS7 - EFAS0 is located on page 04H address
13H, and is incremented once for every receive
frame alignment signal that contains one or more
errors.
There are two maskable interrupts associated with
the frame alignment signal error measurement. FERI
(page 01H, address 1CH) is initiated when the least
significant bit of the errored frame alignment signal
counter toggles, and FERRO (page 01H, address
1DH) is initiated when the counter changes from
FFH to 00H.
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