MT9074AL Zarlink Semiconductor, Inc., MT9074AL Datasheet - Page 21

• Manufacturer Part Number: MT9074AL
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Zarlink Semiconductor, Inc.

Data Sheet
successive read/write operations to the HDLC FIFO
is required.
Table 13 associates the MT9074 control and status
pages with access and page descriptions.
Identification Code
The MT9074 shall be identified by the code
10101111, read from the identification code status
register (page 03H, address 1FH).
ST-BUS Streams
In T1 mode, there is one control and one status ST-
BUS stream that can be used to program / access
channel associated signaling nibbles. CSTo contains
the received channel associated signaling bits, and
for those channels whose Per Time Slot Control
word bit 1 "RPSIG" is set low, CSTi is used to control
the transmit channel associated signaling. The DSTi
and DSTo streams contain the transmit and receive
voice and digital data. Only 24 of the 32 ST-BUS
channels are used for each of DSTi, DSTo, CSTi and
CSTo. In each case individual channel mapping is as
illustrated in Table , “Table 6 - STBUS vs. DS1 to
Channel Relationship(T1),” on page 15.
In E1 mode, the ST-BUS stream can also be used to
access channel associated signaling nibbles. CSTo
contains the received channel associated signaling
bits (e.g., ITU-T R1 and R2 signaling), and for those
channels whose Per Time Slot Control word bit 1
"RPSIG" is set low, CSTi is used to control the
transmit channel associated signaling. The DSTi and
DSTo streams contain the transmit and receive voice
and digital data.
Only 30 of the 32 ST-BUS channels are used for
each of DSTi, DSTo, CSTi and CSTo. In each case
individual channel mapping is as illustrated in Table
10 Time slot to Channel Relationship.
Reset Operation (Initialization)
The MT9074 can be reset using the hardware
RESET pin (see pin description for external reset
circuit requirements) for T1 and (pin 11 in PLCC, pin
84 in MQFP) or the software reset bit RST (page 1H,
address 1AH) for E1/T1.
NOTE: Following a software reset, the device may
insert bipolar violations in the transmit data
stream output on TTIP and TRING. This condition
occurs infrequently upon software reset. Once the
error condition exists, it will continue indefinitely
until the device is reset.
To obtain error free data transmission, it is
recommended that a software routine execute
upon software reset. This routine loops back the
analog signal. If bipolar violations occur, the
device must be reset, and the procedure is
repeated.
This routine shall execute as follows:
(1) Set all registers as per desired operating mode.
(2) Place the device into metallic loopback (set bit
(3) Wait until frame synchronization is achieved.
(4) Clear the Bipolar Violation counters.
(5) Wait 100 milliseconds.
(6) Check for bipolar violation errors. If any occur
reset the device and return to step (1).
When the device emerges from its reset state it will
begin to function with the default settings described
in Table 14 (T1) and Table 15 (E1), all control
registers default to 00H. A reset operation takes 1
full frame (125 us) to complete.
AB/ABCD Bit Debounce
6 address 15H of page 1, in T1 mode - 7.5 dB of
line
programmed).
Error Insertion
Transmit Data
Zero Coding
Line Codes
Loopbacks
Function
Data Link
Interrupts
Signaling
HDLC0,1
Counters
SLC-96
build
Mode
Table 14 - Reset Status(T1)
out
will
also
CAS Registers
Serial Mode
Deactivated
Deactivated
Deactivated
Deactivated
Deactivated
Deactivated
Deactivated
All Ones
masked
Cleared
Status
have
D4
MT9074
to
be
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