MT9074AL Zarlink Semiconductor, Inc., MT9074AL Datasheet - Page 104

• Manufacturer Part Number: MT9074AL
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Zarlink Semiconductor, Inc.

MT9074
104
Bit
7
6
5
4
3
2
1
0
RxFRST RX FIFO Reset. When high, the RX
TxFRST TX FIFO Reset. When high, the TX
TxCRCI Transmit CRC Inhibited. When
INTSEL Interrupt Selection. When high, this
Table 146 - HDLC Control Register 2
CYCLE Cycle. When high, this bit will cause
SEVEN Seven Bit Address Recognition.
Name
RSV
RSV
(Page B & C, Address 15H)
bit will cause bit 2 of the Interrupt
Register to reflect a TX FIFO
underrun (TXunder). When low, this
interrupt will reflect a frame abort
(FA).
the transmit byte count to cycle
through the value loaded into the
Transmit Byte Count Register.
high, this bit will inhibit transmission
of the CRC. That is, the transmitter
will not insert the computed CRC
onto the bit stream after seeing the
EOP tag byte. This is used in V.120
terminal adaptation for synchronous
protocol sensitive UI frames.
When high, this bit will enable seven
bits of address recognition in the first
address byte. The received address
byte must have bit 0 equal to 1 which
indicates a single address byte is
being received.
Reserved, must be zero for normal
operation.
Reserved, must be zero for normal
operation.
FIFO will be reset. This causes the
receiver to be disabled until the next
reception of a flag. The status
register will identify the FIFO as
being empty. However, the actual bit
values in the RX FIFO will not be
reset.
FIFO will be reset. The Status
Register will identify the FIFO as
being empty. This bit will be reset
when data is written to the TX FIFO.
However, the actual bit values of data
in the TX FIFO will not be reset. It is
cleared by the next write to the TX
FIFO.
Functional Description
Bit
7-0
Table 147 - HDLC Interrupt Mask Register
FA:TxUNDE
RIMRxFFIM
RxEOPIM
TxEOPIM
RxOVFIM
RxFEIM
TxFLIM
Name
GaIM
(Page B & C, Address 16H)
This register is used with the
Interrupt Register to mask out
the
required by the microprocessor.
Interrupts that are masked out
will not drive the pin IRQ low;
however,
appropriate bit in the Interrupt
Register. An interrupt is disabled
when the microprocessor writes
a 0 to a bit in this register.
This register is cleared on power
reset.
Functional Description
interrupts
they
that
Data Sheet
will
are
set
not
the