MT9074AL Zarlink Semiconductor, Inc., MT9074AL Datasheet - Page 31

• Manufacturer Part Number: MT9074AL
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Zarlink Semiconductor, Inc.

MT9074
In a multi-trunk slave or loop-timed system (i.e.,
PABX application) a single trunk will be chosen as a
network
described in the previous paragraph. The remaining
trunks will use the system timing derived from the
synchronizer to clock data out of their slip buffers.
Even though the PCM30 signals from the network
are synchronous to each other, due to multiplexing,
transmission impairments and route diversity, these
signals may jitter or wander with respect to the
synchronizing trunk signal. Therefore, the E1.5o
clocks of non-synchronizer trunks may wander with
respect to the C1.50 clock of the synchronizer and
the system bus.
Network standards state that, within limits, trunk
interfaces must be able to receive error-free data in
the presence of jitter and wander (refer to network
requirements for jitter and wander tolerance). The
MT9074 will allow a maximum of 26 channels (208
UI, unit intervals) of wander and low frequency jitter
before a frame slip will occur.
The minimum delay through the receive slip buffer is
approximately two channels and the maximum delay
is approximately 60 channels (see Figure 14).
When the C4b and the E1.5o clocks are not phase-
locked, the rate at which data is being written into the
slip buffer from the PCM30 side may differ from the
rate at which it is being read out onto the ST-BUS. If
this situation persists, the delay limits stated in the
previous paragraph will be violated and the slip
buffer will perform a controlled frame slip. That is, the
buffer pointers will be automatically adjusted so that
a full PCM30 frame is either repeated or lost. All
frame slips occur on PCM30 frame boundaries.
31
Read Pointer
47 CH
Read Pointer
synchronizer,
60 CH
34 CH
512 Bit
Elastic
Store
Write Pointer
Figure 14 - Read and Write Pointers in the Slip Buffers
which
2 CH
28 CH
Read Pointer
Read Pointer
will
15 CH
function
as
-13 CH
13 CH
Two status bits, RSLIP and RSLPD (page03H,
address13H) give indication of a slip occurrence and
direction. RSLIP changes state in the event of a slip.
If RSLPD=0, the slip buffer has overflowed and a
frame was lost; if RSLPD=1, an underflow condition
occurred and a frame was repeated. A maskable
interrupt SLPI (page 01H, address 1BH) is also
provided.
Figure 14 illustrates the relationship between the
read and write pointers of the receive slip buffer.
Measuring clockwise from the write pointer, if the
read pointer comes within two channels of the write
pointer a frame slip will occur, which will put the read
pointer
Conversely, if the read pointer moves more than 60
channels from the write pointer, a slip will occur,
which will put the read pointer 28 channels from the
write pointer. This provides a worst case hysteresis
of 13 channels peak (26 channels peak-to-peak) or a
wander tolerance of 208 UI.
Framing Algorithm
Frame Alignment in T1 Mode
In T1 mode, MT9074 will synchronize to DS1 lines
formatted with either the D4 or ESF protocol. In
either mode the framer maintains a running 3 bit
history of received data for each of the candidate bit
positions. Candidate bit positions whose incoming
patterns fail to match the predicted pattern (based on
the 3 bit history) are winnowed out. If, after a 10 bit
history has been examined, only one candidate bit
position remains within the framing bit period, the
receive side timebase is forced to align to that bit
position. If no candidates remain after a 10 bit
history, the process is re-initiated. If multiple
34
channels
from
Wander Tolerance
the
Data Sheet
write
pointer.