MT9074AL Zarlink Semiconductor, Inc., MT9074AL Datasheet - Page 16

• Manufacturer Part Number: MT9074AL
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Zarlink Semiconductor, Inc.

MT9074
16
The SLC-96 frame structure is similar to the D4
frame structure, except a facility management
overlay is superimposed over the erstwhile Fs bits,
see Table 9.
The protocol appropriate for the application is
selected via the Framing Mode Selection Word,
address 10H of Master Control page 1. In T1 mode
MT9074 is capable of generating the overhead bit
framing pattern and (for ESF links) the CRC
remainder for transmission onto the DS1 trunk. The
beginning of the transmit multiframe may be
determined by any of the following criteria:
(i)It may free - run with the internal multiframe
counters;
(ii)The multiframe counters may be reset with the
external hardware pin TxMF. If this signal is not
synchronous with the current transmit frame count it
may cause the far end to go temporarily out of sync.
(iii) Under software control (by setting the TxSYNC
bit in page 01 address 12H) the transmit multiframe
counters will be synchronized to the framing pattern
present in the overhead bits multiplexed into channel
31 bit 0 of the incoming 2.048 Mb/s digital stream
DSTi. Note that the overhead bits extracted from the
receive signal are multiplexed into outgoing DSTo
channel 31 bit 0.
(iv) In SLC - 96 mode the transmit frame counters
synchronize to the framing pattern clocked in on the
TXDL input.
Frame #
Frame #
Table 8 - ESF Superframe Structure (T1)
10
12
13
14
15
16
17
18
19
20
21
22
23
24
11
Table 7 - D4 Superframe Structure(T1)
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
FPS
0
0
1
0
1
1
Ft
1
0
1
0
1
0
FDL
X
X
X
X
X
X
X
X
X
X
X
X
Fs
0
0
1
1
1
0
CRC
CB1
CB2
CB3
CB4
CB5
CB6
Signaling
Data Sheet
Signaling
A
B
A
B
C
D