MT9074AL Zarlink Semiconductor, Inc., MT9074AL Datasheet - Page 86

• Manufacturer Part Number: MT9074AL
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Zarlink Semiconductor, Inc.

MT9074
86
Table 106 - Most Significant Phase Status Word
2-0
Bit
7
6
5
4
3
RSLPD Receive
RSLIP Receive Slip. A change of state (i.e.,
Name
RXFR
AUXP Auxiliary Pattern. This bit will go high
CEFS Consecutively
- - -
M
(Page 3, Address 13H) (E1)
1-to-0 or 0-to-1) indicates that a
receive controlled frame slip has
occurred.
indicates that the last received frame
slip resulted in a repeated frame, i.e.,
system clock is faster than network
clock. If zero, indicates that the last
received frame slip resulted in a lost
frame, i.e., system clock is slower than
network clock. Updated on an RSLIP
occurrence basis.
Receive Frame Delay. The most
significant bit of the Receive Slip
Buffer Phase Status Word. If zero, the
delay through the receive elastic buffer
is greater than one frame in length; if
one, the delay through the receive
elastic buffer is less than one frame in
length.
when a continuous 101010... bit
stream (Auxiliary Pattern) is received
on the PCM30 link for a period of at
least 512 bits. If zero, auxiliary pattern
is not being received. This pattern will
be decoded in the presence of a bit
error rate of as much as 10-3.
Alignment Signal. This bit goes high
when the last two frame alignment
signals were received in error. This bit
will be low when at least one of the last
two frame alignment signals is without
error.
Unused.
Functional Description
Slip
Direction.
Errored
If
Frame
one,
Table 107 - Least Significant Phase Status Word
7 - 3 RxTS4 - 0 Receive Time Slot. A five bit
2 - 0 RxBC2 - 0 Receive Bit Count. A three bit
6-0 RFA2-8 Receive Frame Alignment Signal
Bit
Bit
Table 108 - Receive Frame Alignment Signal
7
Name
RIU0
Name
(Page 3, Address 14H) (E1)
(Page 3, Address 15H) (E1)
Receive International Use Zero.
This is the bit which is received on
the PCM30 2048 kbit/sec. link in bit
position one of the frame alignment
signal. It is used for the CRC-4
remainder or for international use.
Bits 2 to 8. These bit are received on
the PCM30 2048 kbit/sec. link in bit
positions two to eight of frame
alignment signal. These bits form the
frame alignment signal and should
be 0011011.
counter that indicates the number
of time slots between the receive
elastic buffer internal write frame
boundary and the ST-BUS read
frame boundary. The count is
updated every 250 uS.
counter that indicates the number
of STBUS bit times there are
between the receive elastic buffer
internal write frame boundary and
the ST-BUS read frame boundary.
The count is updated every 250
uS.
Functional Description
Functional Description
Data Sheet