mg84fl54 Megawin Technology, mg84fl54 Datasheet - Page 104

• Manufacturer Part Number: mg84fl54
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

21. Instruction Set
The Instruction Set is fully compatible with that of the standard 8051 except the execution time, i.e., the number
of clock cycles required to execute an instruction. The shortest execution time is just one system clock cycle
(1/SYSCLK) and the longest is 6 system clock cycles (6/SYSCLK).
Prior to introducing the Instruction Set, users should take care the following notes:
Rn
direct
@Ri
#data
#data16 16-bit constant included in instruction.
addr16
addr11
rel
bit
104
Working register R0-R7 of the currently selected Register Bank.
128 internal RAM locations, any I/O port, control or status register.
Indirect internal RAM location addressed by register R0 or R1.
8-bit constant included in instruction.
16-bit destination address. Used by LCALL and LJMP. A branch can be anywhere within the
64K-byte program memory address space.
11-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2K-byte
page of program memory as the first byte of the following instruction.
Signed 8-bit offset byte. Used by SJMP and all conditional jumps. Range is –128 to +127 bytes
relative to first byte of the following instruction.
128 direct bit-addressable bits in internal RAM, any I/O pin, control or status bit.
MG84FL54B Data Sheet
MEGAWIN