mg84fl54 Megawin Technology, mg84fl54 Datasheet - Page 92

• Manufacturer Part Number: mg84fl54
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

DCON (Device Control Register, Address=C0H, SYS_reset=xxx0-0xxx, Read/Write)
Bit7~5: Reserved, always write 0.
Bit4: SRWKP-- Short Remote Wake-up Enable.
Bit3: EP3DIR-- USB Endpoint 3 Direction select.
Bit2~0: Reserved, always write 0.
UADDR (USB Address Register, Address=D8H, SYS/USB_reset=x000-0000, Read/Write)
Bit7: Reserved.
Bit6~0: UADD[6:0]-- USB Function Address.
UPCON (USB Power Control Register, Address=C9H, SYS/USB_reset=0x0x-x000, Read/Write)
Bit7: CONEN-- USB Connect Enable.
Bit6: Reserved.
Bit5: URWU-- USB Remote Wake-Up Trigger.
Bit4~3: Reserved.
Bit2: URST-- USB Reset Flag.
Bit1: URSM-- USB Resume Flag.
Bit0: USUS-- USB Suspend Flag.
92
CONEN
7
7
7
When this bit is set to “1”, the remote wake-up time which device send to upstream host would be about
1~2ms.
When this bit is cleared to “0”, the remote wake-up time which device send to upstream host would be
about 6~7ms. Default is cleared.
When this bit is set to “1”, EP3 will behave as an IN endpoint.
When this bit is cleared to “0”, EP3 will behave as an OUT endpoint. Default is out endpoint.
This register holds the address for the USB function. During bus enumeration, Firmware should write this
register a unique value assigned by the host.
Default is cleared to '0' after reset. Firmware should set '1' to enable connection to upper host/hub.
This bit is set by the firmware to initiate a remote wake-up on the USB bus when CPU is wake-up by
external trigger. It will be cleared by hardware when remote-wakeup is completed. Don't set this bit unless
the function is suspended
Set by hardware when the device detects the USB bus reset. If this bit is set, the chip will generate an
interrupt to uC. It would be cleared by firmware when serving the USB reset interrupt. This bit is cleared
when firmware writes '1' to it.
Set by hardware when the device detects the resume state on the USB bus. If this bit is set, the chip will
generate an interrupt to uC. It would be cleared by firmware when serving the USB resume interrupt. This
bit is cleared when firmware writes '1' to it.
Set by hardware when the device detects the suspend state on the USB bus. If this bit is set, the chip will
generate an interrupt to uC. During the USB suspend interrupt-service routine, firmware should clear this
bit before enter the suspend mode. This bit is cleared when firmware writes '1' to it.
-
-
UADD6
6
6
6
-
-
UADD5
URWU
5
5
5
-
SRWKP
UADD4
MG84FL54B Data Sheet
4
4
4
-
EP3DIR
UADD3
3
3
3
-
UADD2
URST
2
2
2
-
UADD1
URSM
1
1
1
-
UADD0
USUS
0
0
0
-
MEGAWIN