mg84fl54 Megawin Technology, mg84fl54 Datasheet - Page 86

• Manufacturer Part Number: mg84fl54
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

Table 18-1 WDT Prescaler selcect
Note:
18.2. WDT During Idle and Power Down
In the Idle mode, the WIDL bit (WDTCR.3) determines whether WDT counts or not. Set this bit to let WDT keep
counting in the idle mode.
18.3. WDT Automatically Enabled by Hardware
In addition to being initialized by firmware, the WDTCR register can also be automatically initialized at power-up
by the hardware options HWENW, HWWIDL and HWPS[2:0], which should be programmed by a universal
Writer or Programmer or Megawin proprietary Writer (See
18.4. WDT Overflow Period
The WDT overflow period is determined by the formula:
The following table shows the WDT overflow period for CPU running at SYSCLK=6MHz and 12MHz. The period
is the maximum interval for the user to clear the WDT to prevent from chip reset.
Table 18-2 WDT Overflow Period at SYSCLK=6MHz & 12MHz
18.5. Sample Code for WDT
The following Fig 18-2 shows a sample code for WDT.
Condition: SYSCLK=6MHz
86
WDT Overflow Period =
PS2 PS1 PS0
0
0
0
0
1
1
1
1
PS2 PS1 PS0
0
0
0
0
1
1
1
1
WDTCR is a Write-only register, and it can only be reset to its initial value through power-on reset.
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Prescaler value
Prescaler value
2
SYSCLK Frequency
128
256
15
16
32
64
2
4
8
128
256
X 12 X Prescaler
16
32
64
2
4
8
MG84FL54B Data Sheet
SYSCLK=6MHz
131.072 ms
262.144 ms
524.288 ms
16.778 s
1.048 s
2.097 s
4.194 s
8.389 s
4 Hardware
SYSCLK=12MHz
Option).
131.072 ms
262.144 ms
524.288 ms
65.536 ms
1.048 s
2.097 s
4.194 s
8.389 s
MEGAWIN