mg84fl54 Megawin Technology, mg84fl54 Datasheet - Page 94

• Manufacturer Part Number: mg84fl54
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

Bit3: Reserved.
Bit2: UTXD1-- USB Transmit Done Flag for endpoint 1.
Bit1: URXD0-- USB Receive Done Flag for endpoint 0.
Bit0: UTXD0-- USB Transmit Done Flag for endpoint 0.
UIE1 (USB Interrupt Enable Register 1, Address=DCH, SYS/USB_reset=xxxx-xx00, Read/Write)
Bit7~2: Reserved, always write 0.
Bit1: URXIE3-- USB Endpoint 3 Receive Interrupt Enable.
Bit0: UTXIE3-- USB Endpoint 3 Transmit Interrupt Enable.
UIFLG1 (USB Interrupt Flag Register 1, Address=DDH, SYS/USB_reset=xxxx-xx00, Read/Write)
Bit7~2: Reserve.
Bit1: URXD3-- USB Receive Done Flag for endpoint 3.
Bit0: UTXD3-- USB Transmit Done Flag for endpoint 3.
EPINDEX (Endpoint Index Register, Address=F1H, SYS/USB_reset=xxxx-xx00, Read/Write)
Bit7~2: Reserved, always write 0.
Bit1~0: EPINX[1:0]-- Endpoint Index Bits [1:0]
Before accessing the following USB SFRs, firmware should switch the correct value of EPINDEX for
corresponding endpoint. The following figure shows the EPINDEX switch function:
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7
7
This bit is set by hardware when detected a transmit done on endpoint 2. Firmware can read/write-clear on
this bit. This bit is cleared when firmware writes '1' to it.
This bit is set by hardware when detected a transmit done on endpoint 1. Firmware can read/write-clear on
this bit. This bit is cleared when firmware writes '1' to it.
This bit is set by hardware when detected a receive done on endpoint 0. Firmware can read/write-clear on
this bit. This bit is cleared when firmware writes '1' to it.
This bit is set by hardware when detected a transmit done on endpoint 0. Firmware can read/write-clear on
this bit. This bit is cleared when firmware writes '1' to it.
If this bit is set, enables the receive done interrupt for USB endpoint 3 (URXD3). Default is cleared.
If this bit is set, enables the transmit done interrupt for USB endpoint 3 (UTXD3). Default is cleared.
This bit is set by hardware when detected a receive done on endpoint 3. Firmware can read/write-clear on
this bit. This bit is cleared when firmware writes '1' to it. This bit is invalid only if DCON.EP3DIR is set.
This bit is set by hardware when detected a transmit done on endpoint 3. Firmware can read/write-clear on
this bit. This bit is cleared when firmware writes '1' to it. This bit is invalid only if DCON.EP3DIR is unset.
2’b00: Function Endpoint 0.
2’b01: Function Endpoint 1.
2’b10: Function Endpoint 2.
2’b11: Function Endpoint 3.
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6
6
6
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5
5
5
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MG84FL54B Data Sheet
4
4
4
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3
3
3
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2
2
2
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URXIE3
EPINX1
URXD3
1
1
1
UTXIE3
EPINX0
UTXD3
0
0
0
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