mg84fl54 Megawin Technology, mg84fl54 Datasheet - Page 38

• Manufacturer Part Number: mg84fl54
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

11.2.4. Programmable Clock Output from Timer 2
Timer 2 has a Clock-Out Mode (while CP/-RL2=0 & T2OE=1). In this mode, Timer 2 operates as a
programmable clock generator with 50% duty-cycle. The generated clocks come out on P1.0. The input clock,
SYSCLK/2, increments the 16-bit timer (TH2, TL2). The timer repeatedly counts to overflow from a loaded value.
Once overflows occur, the contents of (RCAP2H, RCAP2L) are loaded into (TH2, TL2) for the consecutive
counting. The following formula gives the clock-out frequency:
Note:
How to Program Timer 2 in Clock-out Mode
• Set T2OE bit in T2MOD register.
• Clear C/T2 bit in T2CON register.
• Determine the 16-bit reload value from the formula and enter it in the RCAP2H and RCAP2L registers.
• Enter the same reload value as the initial value in the TH2 and TL2 registers.
• Set TR2 bit in T2CON register to start the Timer 2.
In the Clock-Out mode, Timer 2 rollovers will not generate an interrupt. This is similar to when Timer 2 is used
as a baud-rate generator. It is possible to use Timer 2 as a baud rate generator and a clock generator
simultaneously. Note, however, that the baud-rate and the clock-out frequency depend on the same overflow
rate of Timer 2.
11.2.5. Timer 2 Register
AUXR (Address=8EH, Auxiliary Register)
T2X12: Timer 2 clock source selector.
Set to select SYSCLK as the clock source, and clear to select SYSCLK/12 while C/T2 (T2CON.1)=0 in Capture
Mode and Auto-Reload Mode.
T2CON (Address=C8H, Timer 2 Control Register)
TF2: Timer 2 overflow flag.
Timer 2 overflow flag set by a Timer 2 overflow happens and must be cleared by firmware. TF2 will not be set
when either RCLK=1 or TCLK=1.
EXF2: Timer 2 external flag.
Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX pin and
EXEN2=1. When Timer 2 interrupt is enabled, EXF2=1 will cause the CPU to vector to the Timer 2 interrupt
routine. EXF2 must be cleared by firmware. EXF2 does not cause an interrupt in up/down mode (DCEN = 1).
RCLK: Receive clock flag.
When set, causes the serial port to use Timer 2 overflow pulses for it’s receive clock in modes 1 and 3. RCLK=0
causes Timer 1 overflow to be used for the receive clock.
TCLK: Transmit clock flag.
When set, causes the serial port to use Timer 2 overflow pulses for it’s transmit clock in modes 1 and 3.
TCLK=0 causes Timer 1 overflows to be used for the transmit clock.
38
Clock-out Frequency =
TF2
7
7
(1) Timer 2 overflow flag, TF2, will always not be set in this mode.
(2) For SYSCLK=12MHz, Timer 2 has a programmable output frequency range from 45.7Hz to 3MHz.
-
EXF2
6
6
-
BRADJ0
4 x (65536 – (RCAP2H, RCAP2L))
RCLK
5
5
SYSCLK Frequency
TCLK
MG84FL54B Data Sheet
4
4
-
EXEN2
T2X12
3
3
TR2
2
2
-
C/T2
1
1
-
CP/-RL2
DPS
0
0
MEGAWIN