mg84fl54 Megawin Technology, mg84fl54 Datasheet - Page 31

• Manufacturer Part Number: mg84fl54
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

11. Three 16-bit Timers
The MG84FL54B has three 16-bit Timer/Counters: Timer 0, Timer 1 and Timer 2. Each consists of two 8-bit
registers, THx and TLx (where, x= 0, 1, or 2). All of them can be configured to operate either as timers or event
counters.
In the Timer function, the TLx register is incremented every 12-clock cycle or 1-clock cycle, which is selectable
by firmware. Thus one can think of it as counting clock cycles. When counting every 12 clock cycles, the count
rate is 1/12 of the SYSCLK frequency.
In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding
external input pin- T0, T1, or T2. In this function, the external input is sampled every clock cycle for T0 pin and
T1 pin, and T2 pin. When the samples show a high and then a low, the count is incremented. The new count
value appears in the register when the transition was detected. For Timer 0, Timer 1 and Timer 2, it takes 2
clock cycles to recognize a 1-to-0 transition, so the maximum count rate is 1/2 of the SYSCLK frequency. There
are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at
least once before it changes, it should be held for at least one clock cycle for Timer 0, Timer 1, and Timer 2.
For Timer 0 and Timer 2, in addition to their standard 8051’s timer function, some special new functions are
added in. The following sub-sections will describe these timer/counters in detail.
11.1. Timer 0 and Timer 1
After power-up or reset, the default function and operation of Timer 0 and Timer 1 is fully compatible with the
standard 8051 CPU. The only difference is that besides SYSCLK/12 the user can select an alternate clock
source, the SYSCLK. The bit-7 and bit-6 in AUXR2 provide this selection.
11.1.1. Mode 0: 13-bit Counter
Timer 0 and Timer 1 in Mode 0 look like an 8-bit Counter with a divide-by-32 prescaler. And, Mode 0 operation
is the same for these two timers. Fig 11-1 shows the Mode 0 operation.
In this mode, the Timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it
sets the Timer interrupt flag TFx. The counted input is enabled to the Timer when TRx=1 and either GATE=0 or
/INTx=1. (Setting GATE=1 allows the Timer to be controlled by external input /INTx, to facilitate pulse width
measurements). TRx and TFx are control bits in SFR TCON. The GATE bit is in TMOD. There are two different
GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).
The 13-bit register consists of all 8 bits of THx and the lower 5 bits of TLx. The upper 3 bits of TLx are
indeterminate and should be ignored. Setting the run flag (TRx) does not clear these registers. That is to say the
user should initialize THx an TLx before start counting.
Fig 11-1 Mode 0: 13-bit Counter
MEGAWIN
SYSCLK
SYSCLK
12
/INTx Pin
Tx Pin
GATE
TRx
AUXR2.TxX12=0
AUXR2.TxX12=1
C//T=0
C//T=1
MG84FL54B Data sheet
TLx[4:0]
THx[7:0]
Overflow
TFx
x = 0 or 1
Interrupt
31