mg84fl54 Megawin Technology, mg84fl54 Datasheet - Page 73

• Manufacturer Part Number: mg84fl54
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

STA, the START Flag
When the STA bit is set to enter a master mode, the TWSI hardware checks the status of the serial bus and
generates a START condition if the bus is free. If the bus is not free, then TWSI waits for a STOP condition and
generates a START condition after a delay. If STA is set while TWSI is already in a master mode and one or
more bytes are transmitted or received, TWSI transmits a repeated START condition. STA may be set at any
time. STA may also be set when TWSI is an addressed slave. When the STA bit is reset, no START condition
or repeated START condition will be generated.
STO, the STOP Flag
When the STO bit is set while TWSI is in a master mode, a STOP condition is transmitted to the serial bus.
When the STOP condition is detected on the bus, the TWSI hardware clears the STO flag. In a slave mode, the
STO flag may be set to recover from an bus error condition. In this case, no STOP condition is transmitted to
the bus. However, the TWSI hardware behaves as if a STOP condition has been received and switches to the
defined not addressed slave receiver mode. The STO flag is automatically cleared by hardware. If the STA and
STO bits are both set, then a STOP condition is transmitted to the bus if TWSI is in a master mode (in a slave
mode, TWSI generates an internal STOP condition which is not transmitted), and then transmits a START
condition.
SI, the Serial Interrupt Flag
When a new TWSI state is present in the SISTA register, the SI flag is set by hardware. And, if the TWSI
interrupt is enabled, an interrupt service routine will be serviced. The only state that does not cause SI to be set
is state F8H, which indicates that no relevant state information is available. When SI is set, the low period of the
serial clock on the SCL line is stretched, and the serial transfer is suspended. A high level on the SCL line is
unaffected by the serial interrupt flag. SI must be cleared by firmware. When the SI flag is reset, no serial
interrupt is requested, and there is no stretching on the serial clock on the SCL line.
AA, the Assert Acknowledge Flag
If the AA flag is set to “1”, an acknowledge (low level to SDA) will be returned during the acknowledge clock
pulse on the SCL line when:
If the AA flag is reset to “0”, a not acknowledge (high level to SDA) will be returned during the acknowledge
clock pulse on SCL when:
CR0, CR1 and CR2, the Clock Rate Bits
These three bits determine the serial clock frequency when TWSI is in a master mode. The clock rate is not
important when TWSI is in a slave mode because TWSI will automatically synchronize with any clock frequency,
which is from a master, up to 100 KHz. The various serial clock rates are shown in the following table.
MEGAWIN
1) The own slave address has been received.
2) A data byte has been received while TWSI is in the master/receiver mode.
3) A data byte has been received while TWSI is in the addressed slave/receiver mode.
1) A data has been received while TWSI is in the master/receiver mode.
2) A data byte has been received while TWSI is in the addressed slave/receiver mode.
MG84FL54B Data sheet
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