mg84fl54 Megawin Technology, mg84fl54 Datasheet - Page 41

• Manufacturer Part Number: mg84fl54
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are transmitted/received: 8 data
bits (LSB first). The shift clock source can be selected to 1/12 or 1/2 the system clock frequency by URM0X6
setting in AUXR2 register. Fig 12-3 shows a simplified functional diagram of the serial port in Mode 0.
Transmission is initiated by any instruction that uses SBUF as a destination register. The “write to SBUF” signal
triggers the UART engine to start the transmission. The data in the SBUF would be shifted into the RXD(P3.0)
pin by each raising edge shift clock on the TXD(P3.1) pin. After eight raising edge of shift clocks passing, TI
would be asserted by hardware to indicate the end of transmission. Fig 12-4 shows the transmission waveform
in Mode 0.
Reception is initiated by the condition REN=1 and RI=0. At the next instruction cycle, the Serial Port Controller
writes the bits 11111110 to the receive shift register, and in the next clock phase activates Receive.
Receive enables Shift Clock which directly comes from RX Clock to the alternate output function of P3.1 pin.
When Receive is active, the contents on the RXD(P3.0) pin would be sampled and shifted into shift register by
falling edge of shift clock. After eight falling edge of shift clock, RI would be asserted by hardware to indicate the
end of reception. Fig 12-5 shows the reception waveform in Mode 0.
Fig 12-3 Serial Port Mode 0
MEGAWIN
MG84FL54B Data sheet
41