mg84fl54 Megawin Technology, mg84fl54 Datasheet - Page 48

• Manufacturer Part Number: mg84fl54
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

Table 12-3 Serial Port Mode setting
SM2: Enables the Automatic Address Recognition feature in Modes 2 or 3.
If SM2=1 then Rl will not be set unless the received 9th data bit (RB8) is ‘1’, indicating an address, and the
received byte is a Given or Broadcast Address. In Mode 1, if SM2=1 then Rl will not be activated unless a valid
stop bit was received, and the received byte is a Given or Broadcast Address. In Mode 0, SM2 should be ‘0’.
REN: Serial reception enable bit.
Set by firmware to enable reception. Cleared by firmware to disable reception.
TB8: The 9th transmit data bit.
The 9th data bit that will be transmitted in Modes 2 and 3. Set or cleared by firmware as desired.
RB8: The 9th receive data bit.
In Mode 2 and 3, the 9th data bit that was received. In Mode 1, if SM2=0, RB8 is the stop bit that was received.
In Mode 0, RB8 is not used.
Tl: Transmit interrupt flag.
Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes,
in any serial transmission. Must be cleared by firmware.
Rl: Receive interrupt flag.
Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes,
in any serial reception (except see SM2). Must be cleared by firmware.
SBUF (Address=99H, Serial Buffer Register)
SBUF[7:0]: Data buffer in transmission and reception.
SADDR (Address=A9H, Slave Address Register)
SADDR[7:0]: Device slave address in transmission and reception.
SADEN (Address=B9H, Slave Address Mask Register)
SADEN[7:0]: Device slave address mask register
SADDR register is combined with SADEN register to form Given/Broadcast Address for automatic address
recognition. In fact, SADEN functions as the “mask” register for SADDR register.
PCON (Address=87H, Power Control Register)
SMOD: Double baud rate control bit.
SMOD0: Clear to let SCON.7 function as ‘SM0’, and set to let SCON.7 function as ‘FE’.
AUXR (Address=8EH, Auxiliary Register)
48
SADDR7
SADEN7
SM0, SM1
SBUF7
SMOD
7
7
7
7
7
00
01
10
11
SADDR6
SADEN6
SMOD0
SBUF6
Mode
6
6
6
6
6
0
1
2
3
SADDR5
SADEN5
SBUF5
Shift Register
5
5
5
5
5
Description
8-bit UART
9-bit UART
9-bit UART
-
SADDR4
SADEN4
SBUF4
MG84FL54B Data Sheet
POF
4
4
4
4
4
SADDR3
SADEN3
SBUF3
GF1
SYSCLK/64 or SYSCLK/32
3
3
3
3
3
SYSCLK/12 or SYSCLK/2
Baud Rate
SADDR2
SADEN2
Variable
Variable
SBUF2
GF0
2
2
2
2
2
SADDR1
SADEN1
SBUF1
PD
1
1
1
1
1
SADDR0
SADEN0
SBUF0
IDL
0
0
0
0
0
MEGAWIN