mg84fl54 Megawin Technology, mg84fl54 Datasheet - Page 75

• Manufacturer Part Number: mg84fl54
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

(SISTA) will be 08H. This status code must be used to vector to an interrupt service routine that loads SIDAT
with the slave address and the data direction bit (SLA+W). The SI bit in SICON must then be reset before the
serial transfer can continue.
When the slave address and the direction bit have been transmitted and an acknowledgment bit has been
received, the serial interrupt flag (SI) is set again, and a number of status codes in SISTA are possible. There
are 18H, 20H, or 38H for the master mode and also 68H, 78H, or B0H if the slave mode was enabled (AA=1).
The appropriate action to be taken for each of these status codes is detailed in the following operating flow chart.
After a repeated START condition (state 10H), TWSI may switch to the master receiver mode by loading SIDAT
with SLA+R.
17.2.2. Master Receiver Mode
In the master receiver mode, a number of data bytes are received from a slave transmitter. SICON must be
initialized as in the master transmitter mode. When the start condition has been transmitted, the interrupt service
routine must load SIDAT with the 7-bit slave address and the data direction bit (SLA+R). The SI bit in SICON
must then be cleared before the serial transfer can continue.
When the slave address and the data direction bit have been transmitted and an acknowledgment bit has been
received, the serial interrupt flag (SI) is set again, and a number of status codes in SISTA are possible. They are
40H, 48H, or 38H for the master mode and also 68H, 78H, or B0H if the slave mode was enabled (AA=1). The
appropriate action to be taken for each of these status codes is detailed in the following operating flow chart.
After a repeated start condition (state 10H), TWSI may switch to the master transmitter mode by loading SIDAT
with SLA+W.
17.2.3. Slave Transmitter Mode
In the slave transmitter mode, a number of data bytes are transmitted to a master receiver. To initiate the slave
transmitter mode, SIADR and SICON must be loaded as follows:
SIADR
The upper 7 bits are the address to which TWSI will respond when addressed by a master. If the LSB (GC) is
set, TWSI will respond to the general call address (00H); otherwise it ignores the general call address.
SICON
CR0, CR1, and CR2 do not affect TWSI in the slave mode. ENSI must be set to “1” to enable TWSI. The AA bit
must be set to enable TWSI to acknowledge its own slave address or the general call address. STA, STO, and
SI must be cleared to “0”.
When SIADR and SICON have been initialized, TWSI waits until it is addressed by its own slave address
followed by the data direction bit which must be “1” (R) for TWSI to operate in the slave transmitter mode. After
its own slave address and the “R” bit have been received, the serial interrupt flag (SI) is set and a valid status
code can be read from SISTA. This status code is used to vector to an interrupt service routine, and the
appropriate action to be taken for each of these status codes is detailed in the following operating flow chart.
The slave transmitter mode may also be entered if arbitration is lost while TWSI is in the master mode (see
state B0H).
If the AA bit is reset during a transfer, TWSI will transmit the last byte of the transfer and enter state C0H or C8H.
TWSI is switched to the not-addressed slave mode and will ignore the master receiver if it continues the transfer.
Thus the master receiver receives all 1s as serial data. While AA is reset, TWSI does not respond to its own
slave address or a general call address. However, the serial bus is still monitored, and address recognition may
MEGAWIN
|<------------------------------------------------- Own Slave Address ----------------------------------------------->|
CR2
X
7
7
x
ENSI
X
1
6
6
STA
X
5
5
0
STO
X
4
4
0
MG84FL54B Data sheet
SI
X
0
3
3
AA
X
2
2
1
CR1
X
1
1
x
CR0
GC
0
0
x
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