mg84fl54 Megawin Technology, mg84fl54 Datasheet - Page 43

• Manufacturer Part Number: mg84fl54
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

Fig 12-6 Serial Port Mode 1, 2, 3
12.3. Mode 2 and Mode 3
11 bits are transmitted through TXD, or received through RXD: a start bit (0), 8 data bits (LSB first), a
programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB8) can be assigned the value of 0
or 1. On receive, the 9th data bit goes into RB8 in SCON. The baud rate is programmable to either 1/32 or 1/64
the system clock frequency in Mode 2. Mode 3 may have a variable baud rate generated from Timer 1 or Timer
2.
Fig 12-2 shows the data frame in Mode 2 and Mode 3. Fig 12-6 shows a functional diagram of the serial port in
Mode 2 and Mode 3. The receive portion is exactly the same as in Mode 1. The transmit portion differs from
Mode 1 only in the 9th bit of the transmit shift register.
The “write to SBUF” signal requests the Serial Port Controller to load TB8 into the 9th bit position of the transmit
shit register and starts the transmission. After receiving a transmission request, the UART engine would start
the transmission at the raising edge of TX Clock. The data in the SBUF would be serial output on the TXD pin
with the data frame as shown in Fig 12-2 and data width depend on TX Clock. After the end of 9th data
transmission, TI would be asserted by hardware to indicate the end of data transmission.
Reception is initiated when the UART engine detected 1-to-0 transition at RXD sampled by RCK. The data on
the RXD pin would be sampled by Bit Detector in UART engine. After the end of 9th data bit reception, RI would
be asserted by hardware to indicate the end of data reception and load the 9th data bit into RB8 in SCON
register.
12.4. Frame Error Detection
When used for framing error detection, the UART looks for missing stop bits in the communication. A missing
stop bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of
SCON.7 is determined by SMOD0 bit (PCON.6). If SMOD0 is set then SCON.7 functions as FE. SCON.7
functions as SM0 when SMOD0 is cleared. When SCON.7 functions as FE, it can only be cleared by firmware.
Refer to Fig 12-7.
MEGAWIN
Mode 2
clock source
SYSCLK/2
“0”
2
“1”
Overflow
Timer 2
“1”
“1”
Mode 1, 3
clock source
“0”
“0”
“0”
2
Overflow
Timer 1
“1”
SM1
SMOD
TCLK
RCLK
SM1
1
1
0
0
RCK
MG84FL54B Data sheet
16
16
TX Clock
RX Clock
SM0
SM1
TB8
SBUF
SBUF
Read
Write
80C51 Internal BUS
80C51 Internal BUS
UART engine
TI
RI
STOP-Bit
9th-Bit
RXBUF
TXBUF
SM0
0
1
Serial Port
Interrupt
RB8
TxD P3.1
RxD P3.0
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