mg84fl54 Megawin Technology, mg84fl54 Datasheet - Page 22

• Manufacturer Part Number: mg84fl54
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

7. System Clock
7.1. Programmable System Clock
The system clock (SYSCLK or CPU clock) of the device is programmable and source-selectable. The user can
program the system clock frequency by bits CKS2~CKS0 (CKCON.2 ~ CKCON.0) and select the clock source
by bit CK_SEL (CKCON2.0). The block diagram of system clock is shown below.
Fig 7-1 Block Diagram of System Clock
Note:
7.2. On-chip XTAL Oscillating Driving Control
To reduce the operating power consumption resulted from the XTAL oscillating circuit, a smart driving control
mechanism is designed. The control bit OSCDR0 in CKCON2 is used for the driving control. When powered on,
the bit is 0 that select the maximum driving to easily start the XTAL oscillating. And, after CPU successfully runs
up, the user can program the bit to some values that can keep XTAL oscillating stable. Refer to the following
table for the values.
Table 7-1 Driving Control Setting
7.3. Clock Register
CKCON (Address=C7H, Clock Control Register)
XCKS4~XCKS0: Filled with a proper value according to OSCin, as listed below.
22
XCKS4
7
(1) In the Power down mode, the XTAL oscillating circuit will stop
(2) If user select 48MHz clock source comes from PLL (EN_PLL=CK_SEL=1), the value on system clock
divider (CKS[2:0])
OSCDR0
0
1
XCKS3
PLL_CV
6
XTAL1
XTAL2
should not
CKCON2.EN_PLL
XCKS2
Oscillating
Circuit
5
1MHz~25MHz
1MHz~16MHz
be setting to 000.
XTAL ranges
XCKS1
MG84FL54B Data Sheet
OSCin
4
XCKS[4:0]
PLL
XCKS0
3
CKCON2.CK_SEL
48MHz
1
0
CKS2
2
CLKin
CKS[2:0]
To USB Logic
CKS1
1
(System Clock)
CKS0
0
SYSCLK
MEGAWIN